CMOS substrate RC netlist reduction towards design cycle speed up

Abstract

Integrated circuit substrate crosstalk is an effect with significant impact on design cycle and silicon success. Its accurate simulation comprises a significant design cycle acceleration means. A seamless way to incorporate the substrate crosstalk effect into the simulation is through a netlist describing the electrical behaviour of the substrate. Since such a netlist contains connections between all substrate contacts, it is extremely large for simulators to handle. Therefore it should be reduced, preserving the related accuracy and enabling simulation. In this work a methodology exploiting geometrical and electrical properties of the structure is applied, leading to a practical netlist. This netlist enables rapid simulation providing crucial information versus impact of the substrate crosstalk on system on chip performance.