Abstract

The More than Moore era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration combines multiple chips with different functionalities and from different silicon nodes inside one package, ranging in size from 75mm x 75mm to 175mm x 175mm. But as with any new technology, heterogeneous integration comes with its own set of unique challenges. For starters, package sizes are expected to grow significantly due to the number of components making up each integrated package. The problem: these significantly larger packages would typically require multiple exposure shots to complete the lithography steps for the package. Furthermore, the process of adding multiple redistribution layers (RDL) may cause stress to both the surface and inside of the substrate. Formation changes experienced by the panel, as a result of thermal, high-pressure and other fan-out processes, shift the design location from its nominal coordinates; this causes inaccurate overlay and low-overlay yield in the lithography process. And then there is the matter of tightening resolution requirements. RDL layers in advanced integrated circuit substrates (AICS) will require a resolution of 3µm and will eventually move toward a resolution of 1µm. To address these challenges, and better enable the heterogenous integration process, an extremely large exposure field, fine-resolution lithography solution was proposed to enable packages over 250mm x 250mm without the need for image stitching, while exceeding the overlay and critical dimension uniformity requirements for these packages. In this paper, a 515mm x 510mm Ajinomoto build-up film (ABF)+copper clad laminate (CCL) substrate is selected as the test vehicle. We will analyze the pattern distortion of an ABF+CCL substrate to understand the distribution of translation, rotation, scale, magnification, trap, orthogonality and other errors in the substrate, and then use an extremely large exposure field, fine-resolution lithography system to address the pattern distortion of the substrate. This demonstration will provide an analysis of panel distortion and detail how the extremely large exposure field, fine-resolution lithography solution addresses panel distortion to achieve an aggressive overlay number.

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