Integrated Circuit Manufacturing Research Articles

Mitigating the Impact of Asymmetric Deformation on Advanced Metrology for Photolithography

Controlling overlay in lithography is crucial for improving the yield of integrated circuit manufacturing. The process disturbances can cause undesirable morphology changes of overlay targets (such as asymmetric grating), which can significantly impact the accuracy of overlay metrology. It is essential to decouple the overlay target asymmetry from the wafer deformation, ensuring that the overlay metrology is free from the influence of process-induced asymmetry (e.g., grating asymmetry and grating imbalance). Herein, we use an asymmetric grating as a model and show that using high-diffraction-order light can mitigate the impact of asymmetric grating through the rigorous coupled-wave analysis (RCWA) method. In addition, we demonstrate the diffraction efficiency as a function of the diffraction order, wavelength, and pitch, which has guiding significance for improving the measurement accuracy of diffraction-based overlay (DBO) metrology.

Formation of Si nanopillars through partial sacrificing in super passivation reactive ion etching

The vertical gate-all-around (VGAA) metal-oxide-semiconductor field-effect transistor (MOSFET) holds remarkable potential in the three-dimensional (3D) integrated circuits (ICs), primarily owing to its capacity for vertical integration. The Si nanopillar, a crucial channel in the VGAA MOSFET, is conventionally shaped via the reactive ion etching (RIE) system employing SF6/O2. Past studies have indicated that high O2 gas conditions in RIE often result in Si grasses irregular nanostructures, such as nanospikes on the bottom surface, due to over-passivation. However, this study revealed that ultrahigh O2 proportions (>70%), especially when combined with low chamber pressure, inhibit the development of Si grasses in the RIE system (termed as super passivation). Nevertheless, this scenario leads to the segmentation of the Si nanopillar. To address this issue, a proposed partial sacrificing method, achieved by sacrificing the upper segment of the nanopillar through prolonged processing time and reduced mask size, successfully yielded Si nanopillars without Si grasses. Furthermore, an empirical model was developed to elucidate how experimental parameters influence etching characteristics, encompassing etching rate and Si nanopillar shape, through a systematic examination of the RIE etching process. This research significantly contributes to the production of VGAA MOSFETs and 3D ICs.

Organ-on-a-Chip: Ubi sumus? Fundamentals and Design Aspects.

This review outlines the evolutionary journey from traditional two-dimensional (2D) cell culture to the revolutionary field of organ-on-a-chip technology. Organ-on-a-chip technology integrates microfluidic systems to mimic the complex physiological environments of human organs, surpassing the limitations of conventional 2D cultures. This evolution has opened new possibilities for understanding cell-cell interactions, cellular responses, drug screening, and disease modeling. However, the design and manufacture of microchips significantly influence their functionality, reliability, and applicability to different biomedical applications. Therefore, it is important to carefully consider design parameters, including the number of channels (single, double, or multi-channels), the channel shape, and the biological context. Simultaneously, the selection of appropriate materials compatible with the cells and fabrication methods optimize the chips' capabilities for specific applications, mitigating some disadvantages associated with these systems. Furthermore, the success of organ-on-a-chip platforms greatly depends on the careful selection and utilization of cell resources. Advances in stem cell technology and tissue engineering have contributed to the availability of diverse cell sources, facilitating the development of more accurate and reliable organ-on-a-chip models. In conclusion, a holistic perspective of in vitro cellular modeling is provided, highlighting the integration of microfluidic technology and meticulous chip design, which play a pivotal role in replicating organ-specific microenvironments. At the same time, the sensible use of cell resources ensures the fidelity and applicability of these innovative platforms in several biomedical applications.

FATE: A Flexible FPGA-Based Automatic Test Equipment for Digital ICs

The limits of chip technology are constantly being pushed with the continuous development of integrated circuit manufacturing processes and equipment. Currently, chips contain several billion, and even tens of billions, of transistors, making chip testing increasingly challenging. The verification of very large-scale integrated circuits (VLSI) requires testing on specialized automatic test equipment (ATE), but their cost and size significantly limit their applicability. The current FPGA-based ATE is limited in its scalability and support for few test channels and short test vector lengths. As a result, it is only suitable for testing specific chips in small-scale circuits and cannot be used to test VLSI. This paper proposes a low-cost hardware and software solution for testing digital integrated circuits based on design for testability (DFT) on chips, which enables the functional and performance test of the chip. The solution proposed can effectively use the resources within the FPGA to provide additional test channels. Furthermore, the round-robin data transmission mode can also support test vectors of any length and it can satisfy different types of chip test projects through the dynamic configuration of each test channel. The experiment successfully tested a digital signal processor (DSP) chip with 72 scan test pins (theoretically supporting 160 test pins). Compared to our previous work, the work in this paper increases the number of test channels by four times while reducing resource utilization per channel by 37.5%, demonstrating good scalability and versatility.

Method for optical proximity correction based ona vector imaging model.

Optical proximity correction (OPC) has become an indispensable step in integrated circuit manufacturing. It requires a huge amount of calculation to obtain a sufficiently accurate OPC model and implement pattern correction. In this paper, the authors proposed an edge-based OPC method built on a vector imaging model, where the analytical correlation between the cost function and movement of each edge segment is established by the chain rule. First, the mask pattern is segmented and downsampled to get the mask image in order to reduce the total data. Second, the aerial image, various parameters on each evaluating point, and the final cost value are obtained in proper sequence. In each part of the OPC process, the procedures of solution and derivation are both recorded. After obtaining the cost value, the chain rule is applied, by which the differential relation between the cost value and movement of each segment is built. According to this differential relation, the next movement of each segment is decided under a quasi-Newton method. All results obtained by the proposed method are compared with results from commercial software. The comparison shows that the proposed OPC method has good OPC accuracy in few iterations.

SCAPSM: attenuated phase-shift mask structure for EUV lithography.

The attenuated phase-shift mask (Att. PSM) is proven to be a promising resolution enhancement technology (RET) to improve the imaging performance in extreme ultraviolet (EUV) lithography. However, due to the reflective nature of the mask structure, the serious shadowing effect can affect the diffraction near field of the mask intensely and further impact the lithography imaging. With the purpose of improving the contrast of lithography imaging, a novel structure of the Att. PSM, to the best of our knowledge, is proposed in this paper. By introducing an absorbent sidewall along the edge of the mask absorber, the diffraction and shadowing effects can be mitigated. By applying the Kirchhoff approximation of mask diffraction, the ability of the novel structure to improve imaging performance is theoretically analyzed. Additionally, these analyses are confirmed by rigorous lithography simulations. The simulation results demonstrate that the proposed mask structure can improve the imaging contrast of EUV lithography, which has potential usage in advanced integrated circuit (IC) manufacturing.

Fluorinated MOF‐Based Hexafluoropropylene Nanotrap for Highly Efficient Purification of Octafluoropropane Electronic Specialty Gas

AbstractHigh‐purity octafluoropropane (C3F8) electronic specialty gas is a key chemical raw material in semiconductor and integrated circuit manufacturing industry, while selective removal of hexafluoropropylene (C3F6) impurity for C3F8 purification is essential but a challenging task. Here we report a fluorinated cage‐like MOF Zn‐bzc‐CF3 (bzc=5‐(trifluoromethyl)‐1H‐pyrazole‐4‐carboxylic acid) for C3F6/C3F8 separation. The incorporation of −CF3 groups not only provides suitable pore aperture size for highly efficient size‐exclusive C3F6/C3F8 separation, but also creates hydrophobic microenvironments, endowing Zn‐bz‐CF3 high chemical stability. Remarkably, Zn‐bzc‐CF3 exhibits high C3F6 adsorption capacity while excluding C3F8, achieving ideal molecular‐sieving C3F6/C3F8 separation. Breakthrough experiments show that Zn‐bzc‐CF3 can efficiently separate C3F6/C3F8 mixture and high‐purity C3F8 (99.9 %) can be obtained.

Fluorinated MOF-Based Hexafluoropropylene Nanotrap for Highly Efficient Purification of Octafluoropropane Electronic Specialty Gas.

High-purity octafluoropropane (C3F8) electronic specialty gas is a key chemical raw material in semiconductor and integrated circuit manufacturing industry, while selective removal of hexafluoropropylene (C3F6) impurity for C3F8 purification is essential but a challenging task. Here we report a fluorinated cage-like MOF Zn-bzc-CF3 (bzc=5-(trifluoromethyl)-1H-pyrazole-4-carboxylic acid) for C3F6/C3F8 separation. The incorporation of -CF3 groups not only provides suitable pore aperture size for highly efficient size-exclusive C3F6/C3F8 separation, but also creates hydrophobic microenvironments, endowing Zn-bz-CF3 high chemical stability. Remarkably, Zn-bzc-CF3 exhibits high C3F6 adsorption capacity while excluding C3F8, achieving ideal molecular-sieving C3F6/C3F8 separation. Breakthrough experiments show that Zn-bzc-CF3 can efficiently separate C3F6/C3F8 mixture and high-purity C3F8 (99.9 %) can be obtained.

Simultaneous Determination of Young's Modulus and Density of Ultrathin Low‐k Films Using Surface Acoustic Waves

The nondestructive testing (NDT) of mechanical properties in ultrathin low dielectric constant (low‐k) films is a major challenge in integrated circuit manufacturing. Young's modulus and density are closely related parameters for low‐k films. This study presents a method for NDT of Young's modulus and density of porous low‐k black diamond (SiOC:H, BD) films. A linear frequency modulation (LFM) surface acoustic wave (SAW) interdigital transducer (IDT) with a frequency range of 20–250 MHz is designed to generate SAW signals on the samples. The series of SAW waveforms obtained on the samples are processed to obtain experimental SAW dispersion curves across a broad frequency range. By comparing these experimental curves with theoretical dispersion curves, as well as their first‐order derivatives, Young's modulus and density of porous low‐k BD films with thicknesses of 100, 300, 500, and 1000 nm are characterized. To verify Young's modulus measurements from the SAW method, a control experiment using nanoindentation is conducted. The results demonstrate that the SAW method can reduce the impact of the substrate and is independent of the film thickness. This study presents a highly accurate measuring method for simultaneous multiparameter evaluation of ultra‐thin low‐k films.

Silatrane-Based Molecular Nanolayers as Efficient Diffusion Barriers for Cu/SiO2/Si Heterojunctions: Implications for Integrated Circuit Manufacturing

Silatrane-Based Molecular Nanolayers as Efficient Diffusion Barriers for Cu/SiO₂/Si Heterojunctions: Implications for Integrated Circuit Manufacturing

Intellectual Property and Security in the Integrated Circuits Industry

The production of integrated circuits (IC) is key to the development of the world economy. The system of intellectual property offers different means of protection for the products of the IC industry. Those are mainly the patents for inventions, registration of topologies of ICs, trade secrets, copyright. The economics of the IC industry in the late 20th century moves different processes in different regions of the world. This economic reality provides an opportunity for those companies to invest heavily in R&D, to create valuable intellectual property and to develop a competitive advantage. The historical development of integrated circuit manufacturing, the development of the main companies involved in the sector and the existing supply chains, raise a number of questions that are related to the concentration of innovation and intellectual property, the potential problems for global supply and economic development, as well as the steps towards overcoming those problems.

Intellectual Property Protection for Integrated Circuits

The intellectual property (IP) protection of integrated circuits (ICs) is of key importance as the semiconductor industry has become a vital part of the advancement of technology and the development of the global economy. This is made clear by the creation of a special IP sui generis right that is meant to protect the layout design of ICs and make them harder to copy. The present article will present an overview of protection of layout designs of ICs and the experience of leading countries in the production of semiconductors. The countries are chosen based on their patenting activity in field which is an indicator of scientific and financial effort of those nations to develop their IC production capabilities.

Research on Parallel Reading and Drawing Techniques for Chemical Mechanical Polishing Simulation Data Based on Multi-Thread

In advanced integrated circuit manufacturing, the quality of chemical mechanical polishing (CMP) is a key factor affecting chip performance and yield. Designers need to use CMP simulation tools to locate and analyze the defects in the layout after the CMP process. However, the advancement of process nodes and the increase in data volume presents a great challenge to the speed of graphical display of CMP simulation data. To solve this issue, we propose a solution that uses multi-threading technology to optimize both data reading and drawing. In the process of data reading, we employ OpenMP and memory mapping (Mmap) technology to achieve parallel reading of file segmentation and propose a fast-string conversion algorithm based on the properties of simulation data. In the process of data drawing, we propose an adaptive downsampling method for data graphical display that combines multi-threading and double buffering technology to enable the parallel drawing of layouts. The effectiveness of this method is verified by testing CMP simulation data of various scales. Compared to traditional methods, this approach improves reading efficiency by over 8 times and drawing efficiency by more than 10 times. Furthermore, it enhances the smoothness of interaction with the CMP simulation tool.

Improving Recognition of Defective Epoxy Images in Integrated Circuit Manufacturing by Data Augmentation

This paper discusses the problem of recognizing defective epoxy drop images for the purpose of performing vision-based die attachment inspection in integrated circuit (IC) manufacturing based on deep neural networks. Two supervised and two unsupervised recognition models are considered. The supervised models examined are an autoencoder (AE) network together with a multi-layer perceptron network (MLP) and a VGG16 network, while the unsupervised models examined are an autoencoder (AE) network together with k-means clustering and a VGG16 network together with k-means clustering. Since in practice very few defective epoxy drop images are available on an actual IC production line, the emphasis in this paper is placed on the impact of data augmentation on the recognition outcome. The data augmentation is achieved by generating synthesized defective epoxy drop images via our previously developed enhanced loss function CycleGAN generative network. The experimental results indicate that when using data augmentation, the supervised and unsupervised models of VGG16 generate perfect or near perfect accuracies for recognition of defective epoxy drop images for the dataset examined. More specifically, for the supervised models of AE+MLP and VGG16, the recognition accuracy is improved by 47% and 1%, respectively, and for the unsupervised models of AE+Kmeans and VGG+Kmeans, the recognition accuracy is improved by 37% and 15%, respectively, due to the data augmentation.

Development frontier and future challenges of lithography machines for integrated circuit manufacturing

Development frontier and future challenges of lithography machines for integrated circuit manufacturing

Analysis and Research on the Impact of Digital Transformation and Upgrading of China’s Manufacturing Industry on Global Supply Chains

Abstract The profound impact of the digital transformation and upgrading of China’s manufacturing industry on the global supply chain forms the core of this analysis. This paper introduces a measurement model for assessing the manufacturing digital transformation and upgrading, which includes constructing an indicator system and calculating the weights of these indicators using the entropy value method. Subsequently, the raw data for each indicator are processed through the maximum-minimum value method. Furthermore, this study advances a global supply chain performance assessment SCOR model tailored to the specifics of manufacturing digital transformation and upgrading. It conducts a quantitative analysis of key indicators, typically challenging to quantify, thus deriving their numerical expressions and examining the effects of performance changes. In 2023, China’s comprehensive index for transformation and upgrading escalated to 83.84%, a significant increase from 6.78% in 1999. In a simulation experiment focusing on the integrated circuit manufacturing industry, the digital transformation and upgrading of China’s manufacturing sector is shown to enhance production inventory levels within the global supply chain and reduce delivery times. The Estimated Lead Time (ELT) service level improved by 5%, reaching 100%. At the same time, revenues and profits saw increments of approximately 44.66 million and 32.11 million US dollars, respectively, relative to scenarios absent of such digital advancements.

Cell chip device for real-time monitoring of drug release from drug-laden microparticles.

A cell chip is a microfluidic cell culture device fabricated using microchip manufacturing methods for culturing living cells in a micrometer-sized chamber to model the physiological functions of tissues and organs. It has been extensively investigated in the domain of drug transport and toxicity research. Herein, we developed a cell chip for real-time monitoring of drug release from drug carriers. The proposed system integrates three core functions: cell culture, real-time analysis, and drug delivery tests. This device was designed to be loaded with microparticles for drug release and to enable real-time drug measurement. The efficacy of the developed system was evaluated by measuring the concentration of drugs released from the microparticles prepared with poly(lactic-co-glycolic acid) (PLGA). Doxorubicin, an anticancer drug, was used as a model drug and A549 cells, a type of lung cancer cell, were simultaneously cultured to compare the drug release concentrations in the presence of cells. Furthermore, variations in cell viability with respect to the presence of drug-loaded microparticles were observed and analyzed. Notably, as the proposed system requires an extremely small number of microparticles, it affords simple implementation in a single device, thereby eliminating the need for complex accessories and instruments for analysis. Thus, the analysis process becomes more convenient and cost-efficient. Thus, the proposed method offers an easy analysis of the release behavior of various cells and drugs. The simplicity and low cost of this innovative system without sacrificing analytical precision demonstrate its potential for applications across various fields.

Advanced Integrated Circuit Manufacturing Technology Process Industry Development

Integrated circuits are circuits with specific functions that are integrated together by semiconductor processes and are a new type of semiconductor device developed in the late 1950s through the 1960s. Integrated circuits are the foundation of information development and the benchmark for high quality development of national economy. This paper introduces the concept of integrated circuits as well as the integrated circuit process, and the application areas of integrated circuits, which account for an expanding and growing share of information, communication, consumer electronics, automotive electronics, medical electronics and other consumer areas. It discusses China's future IC process development path by combining the IC production process and design process, industrial development, design process and preparation limitations, and proposes relevant suggestions and strategies by speculating on the future development of the process.

A fine-grained detection method for gate-level hardware Trojan based on bidirectional Graph Neural Networks

Due to technical barriers and economic costs, malicious circuits, known as hardware Trojans, are easily implanted in the complicated integrated circuit design and manufacturing process, which can lead to many disastrous consequences, such as denial of service, information leakage, performance degradation, etc. Research on how to detecting hardware Trojans has grown into a significantly open issue over the past decade. While, for very large scale integrated circuits, numerous new challenges deserve our full attention, including golden-free chip reference, automatic feature engineering, hardware Trojan localization, and scalable framework. In response to the above challenges, a fine-grained gate-level hardware Trojan detection approach is proposed in this paper, named GateDet, from improving earlier circuit graph modeling to developing a detection framework based on Bidirectional Graph Convolution Networks with a timely information fusion strategy. GateDet achieves automatic feature circuit extraction and further overcomes the original neighborhood limitation of Bidirectional Graph Convolution Network. Moreover, for large-scale training, it comprehensively considers the problems of sample imbalance and boundary network, and develops a circuit directed graph sampling method based on GraphSAINT, which improves the training performance of the directed graph framework. From experiments, GateDet shows high scalability on 24 benchmarks of TrustHub. It could be used to learn about adaptive structural feature extraction for different Trojans simultaneously. Compared to the existing gate-level detections, the fine-grained results of GateDet are more accurate and can be used to track suspicious structures, reducing manual review.

Anti-crosstalk absolute phase retrieval method for microscopic fringe projection profilometry using temporal frequency-division multiplexing.

In microscopic fringe projection profilometry (MFPP), the traditional absolute phase retrieval method using composite frequency fringe has the shortcomings of low accuracy and poor robustness due to mutual crosstalk of harmonic from the different channels of frequency-division multiplexing. In this study, an absolute phase retrieval method that avoids the inter-channel crosstalk is proposed. By introducing guard bands to accommodate the frequency channels corresponding to the second harmonic that dominate the high order harmonics, the aliasing between the second harmonic and the fundamental is eliminated. Consequently, phase maps without crosstalk can be demodulated using appropriate phase-shifting algorithms. The proposed method is well-suited for high-precision three-dimensional shape measurement scenarios in many fields such as integrated circuit manufacturing process control and micro-electro-mechanical system quality inspection. The experiment results demonstrate that the anti-crosstalk method is effective and can realize three-dimensional reconstruction for discontinuous planar surface and spherical surface.