Integrated Circuit Packaging Research Articles

Improvement of Manufacturing Yield Through Gemba Approach: A Case Study in an Integrated Circuit Package Assembler Company

Improvement of Manufacturing Yield Through Gemba Approach: A Case Study in an Integrated Circuit Package Assembler Company

Improvement of Manufacturing Yield through Gemba Approach: A Case Study in an Integrated Circuit Package Assembler Company

Improvement of Manufacturing Yield through Gemba Approach: A Case Study in an Integrated Circuit Package Assembler Company

Wire Bond Ability Enhancement of 8 Leads Small Outline Integrated Circuit and 14 Leads Thin Shrink Small Outline Package Using AuPd Coated Cu Wire Bonding for Automotive Devices

Paper present a study enhancement of wire bonding process in the integrated circuit package with 2N AuPd coated Cu wire (2N-AuPdCu) for Automotive devices. Wire bonding is the electrical connection between pad and leadframe. In present, Au wire is recently use for interconnection while the gold price still exorbitant and caused concern to the wire bonding cost. Cu wire is a lower price and considered to be an alternative for the interconnection but still concern in term of corrosion and reliability. Recently, 4N AuPd coated Cu wire (4N-AuPdCu) material have been introduced for automotive device but still encounter the reliability problem. The 2N AuPd coated Cu wire was developed version for more reliability enhancement and consider to use for alternative wire of automotive device. In the experiment, Au wire, 4NAuPdCu wire and 2N AuPd coated Cu wire were used for wire bonding process on 8 leads Small Outline Integrated Circuit Package (8L-SOIC) and 14 leads Thin Shrink Small Outline Package (14L-TSSOP) to compare wire bond ability. Analysis, this package tested wire bond ability and reliability. The results performed well in wire bond ability and reliability for 2N AuPd coated Cu wire when comparing with Au wire and 4N AuPd coated Cu wire. Therefore, 2N AuPd coated Cu wire can enhance the quality and reliability for 8L-SOIC package and 14L-TSSOP package for automotive device.

Preparation and study on electrical/thermal properties of epoxy/polyacrylate rubber composite dielectric

AbstractWith the development of power systems and electronic devices, epoxy resin (EP) is facing increasingly severe operating environments, and its performance may not meet expectations. In order to broaden the application of EP, the DE/EP composite films were prepared with EP as matrix, polyacrylic rubber dielectric elastomer (DE) as reinforcement materials. The structure of DE/EP composite films was characterized by XRD, SEM, and other methods, and the electrical and thermal properties of the materials were tested and studied. The study found that with appropriate dissolution and stirring treatment, DE can be evenly dispersed in the EP matrix, and the introduction of DE does not significantly affect the structure of the EP molecular chain, also found the introduction of DE improve the electrical and thermal properties of EP. The breakdown strength of the 4% DE/EP composite film surpasses that of the pure EP film by 15.58%. Additionally, the thermal conductivity of the 8% DE/EP composite film is elevated by 41.6% compared to the pure EP film, while its dielectric constant is also enhanced by 8.2%. This work may provide a theoretical basis for studying the application of EP modified system in electrical engineering, integrated circuit packaging and other fields.

Integrated Circuit Packaging Defect Analysis and Deep Learning Detection Method

Integrated Circuit Packaging Defect Analysis and Deep Learning Detection Method

Investigation of Effects of Porosity and Coarsening on Thermal and Mechanical Properties of Sintered Silver Die Attachment

Investigation of Effects of Porosity and Coarsening on Thermal and Mechanical Properties of Sintered Silver Die Attachment

Atomic-Scale Investigation of Electromigration Behavior in Cu-to-Cu Joints at High Current Density

Three-dimensional integrated circuit (3D IC) packaging offers significant advantages, such as enhanced computational efficiency through greater integration and shorter interconnection distances. The effective interconnection of layers, particularly through redistribution layer (RDL) technology, is crucial for the successful operation of 3D ICs. While copper remains the preferred material for interconnections, often in conjunction with through-silicon via (TSV) technology for chip-to-chip links, the shrinking dimensions of components present challenges. In particular, the reduction in size may lead to elevated current densities in individual joints, giving rise to issues like electromigration (EM) and potential failure. EM-induced atomic migration may lead to the formation of voids in the interconnection. The accumulation of voids to a critical point may result in an open circuit in the joints, significantly impacting the conductor's reliability. This work delves into the micro-scale aspects of these challenges, complementing previous macroscopic investigations. We aim to elucidate the behavioral mechanisms through atomic-scale observations, employing an in-situ high-resolution transmission electron microscope (in-situ HRTEM) to observe atomic-scale images of EM. The insights gained from this work not only contribute to the academic understanding of industry challenges but hold potential applications in real-world manufacturing processes. Fig. 1. (a) Schematic diagram of TEM sample preparation. (b) Cross-sectional HRTEM image of copper bonding. (c, d) TEM images showing voids expansion at bonding interface. Figure 1

Microfluidic Lab-on-CMOS Packaging Using Wafer-Level Molding and 3D-Printed Interconnects.

Lab-on-a-chip (LoC) technologies continue to promise lower cost and more accessible platforms for performing biomedical testing in low-cost and disposable form factors. Lab-on-CMOS or lab-on-microchip methods extend this paradigm by merging passive LoC systems with active complementary metal-oxide semiconductor (CMOS) integrated circuits (IC) to enable front-end signal conditioning and digitization immediately next to sensors in fluid channels. However, integrating ICs with microfluidics remains a challenge due to size mismatch and geometric constraints, such as non-planar wirebonds or flip-chip approaches in conflict with planar microfluidics. In this work, we present a hybrid packaging solution for IC-enabled microfluidic sensor systems. Our approach uses a combination of wafer-level molding and direct-write 3D printed interconnects, which are compatible with post-fabrication of planar dielectric and microfluidic layers. In addition, high-resolution direct-write printing can be used to rapidly fabricate electrical interconnects at a scale compatible with IC packaging without the need for fixed tooling. Two demonstration sensor-in-package systems with integrated microfluidics are shown, including measurement of electrical impedance and optical scattering to detect and size particles flowing through microfluidic channels over or adjacent to CMOS sensor and read-out ICs. The approach enables fabrication of impedance measurement electrodes less than 1 mm from the readout IC, directly on package surface. As shown, direct fluid contact with the IC surface is prevented by passivation, but long-term this approach can also enable fluid access to IC-integrated electrodes or other top-level IC features, making it broadly enabling for lab-on-CMOS applications.

Degradation in Electrothermal Characteristics and Failure Mechanism of SiC JBS With Different Die Attach Materials Under 300 ∘C Power Cycle Stress

Degradation in Electrothermal Characteristics and Failure Mechanism of SiC JBS With Different Die Attach Materials Under 300 ^∘C Power Cycle Stress

Analysis of warpage and reliability of very thin profile fine pitch ball grid array

With the evolution of advanced integrated circuit (IC) packaging technology, the use of experiments to identify package performance and life expectation will take a significant amount of time and cost to finish the job. To reduce the cost of research and testing, predictive analyses of reliability and performance using simulation tools have become a feasible approach for the IC assembly industry. Therefore, this study utilized Moldex3D molding simulation software to analyze very thin profile fine pitch ball grid array (VFBGA) packages and established a numerical analysis procedure from the molding and curing process, the post-mold cure (PMC) process, to a thermal cycling test (TCT) to predict the amount of package warpage during processing and reliability after TCT.The results showed that the warpage trends of both experiments and simulations during the same temperature ramping process were similar. In the thermal cycling analysis, potential failure locations were found to be at the copper pillars and redistribution layer (RDL), where the maximum Von Mises stress occurred at the lowest temperature (−65 °C). The fatigue life model, Coffin–Manson model, was used to calculate the potential fatigue life at the two locations, resulting in 1689 cycles (copper pillars) and 9706 cycles (RDL L1).

Evaluation of Taiwan's IC industry production and market efficiencies under the consideration of corporate social responsibility

AbstractTaiwan has a complete semiconductor industry chain and is important in global semiconductor manufacturing. In addition to considering operational conditions, companies have also attached importance to corporate social responsibility (CSR) in recent years. This research thus takes 60 integrated circuit (IC) companies in Taiwan as a research sample and adopts the Meta Two‐stage dynamic RDM DDF (range directional model directional distance function) under an exogenous CSR model to explore their market stage efficiency and production stage efficiency. This study aimed to analyze whether incorporating a company's CSR performance into performance evaluations affects the production and profitability efficiency of Taiwanese IC companies. The findings are as follows: Most IC companies practice CSR and demonstrate good CSR performance. The market stage efficiency and production stage efficiency of the IC packaging and testing group are better than those of other groups.

Efficiency Analysis of Die Attach Machines Using Overall Equipment Effectiveness Metrics and Failure Mode and Effects Analysis with an Ishikawa Diagram

Efficiency Analysis of Die Attach Machines Using Overall Equipment Effectiveness Metrics and Failure Mode and Effects Analysis with an Ishikawa Diagram

A compact self-powered inductor-less piezoelectric energy harvesting circuit using gyrator

In traditional low-frequency energy harvesting circuits, a large matched inductor with a large size is unavoidable. To reduce the size of the circuit, this paper proposes a compact self-powered inductor-less high-efficiency piezoelectric energy harvesting circuit using a low-power-consumption gyrator. A self-powered floating gyrator inductor is used in place of an inductor in the proposed circuit, and the required phasor response is acquired by using its voltage–current (V–I) relationship. The proposed circuit offers easy adjustability and performance benefits in small integrated circuits packages. The proposed circuit can be cost-effective and provide reduced area advantages in autonomous self-powered Internet-of-Things and wireless sensor nodes applications. Regarding harvested energy, the proposed circuit with a storage capacitor of 0.24 F can obtain 320% improved performance than standard energy harvesting along with the lowest power consumption of 0.25 µW in self-powered operation. The proposed technique can also be applied to similar piezoelectric energy harvesting strategies with large inductors.

Thermal-Mechanical Property of High Aspect Ratio TSV in Advanced IC integration and Packaging

Advanced packaging of integrated circuits (IC) plays a critical role on the way towards high performance, high density, low power consumption and light weight of electronics. Through-silicon vias (TSV) is the heart of 3D IC integration and packaging. However, copper protrusion due to mismatch of coefficients of thermal expansion (CTE) between copper and silicon, which may result in the dielectric material breakdown, becomes the bottleneck of TSV in high-temperature application. In this paper, thermal-mechanical property of high aspect ratio TSV is investigated through experiments under different annealing process, which will help to accelerate the widely application of TSV in advanced packaging of electronics in the future.

Enhancing Semiconductor Package Reliability through Mechanical Property Optimization of Pressureless Sintering Die Attach Adhesives

There is growing demand for high-power devices, wide bandgap SiC and GaN semiconductor materials in semiconductor market, and a drive to integrate die attach materials that can replace lead-containing solders. However, epoxy-based and solder materials face challenges to meet high thermal conductivity and survive elevated working temperatures. Pressure-assisted silver sintering has overcome these challenges, but downsides of pressure-assisted silver sintering are that it requires special equipment and for some applications, packages are unable to withstand the pressure required to facilitate sintering. Pressureless sintering materials could be processed using the same equipment as traditional die attach adhesives. It develops strong metal bonds to substrates, providing high thermal conductivity and withstanding high temperatures. However, compared to pressure-assisted sintering, pressureless materials may have difficulties to form a dense bondline structure if the formulation design is not optimized. Moreover, once the sintered structure is built during cure, further bondline reduction may induce additional stress. Therefore, it is critical that the pressureless sintering material’s mechanical properties are formulated to effectively manage stress and pass all reliability testing – especially for automotive packages. This paper will present the findings from a study that evaluated the impact of various formulation components – such as silver packing and resin chemistry – on the mechanical properties and interfacial bonding of pressureless sintering die attach adhesives. The effect on in-package reliability performance was also investigated to better understand material properties that can pass reliability testing while maintaining high thermal and electrical conductivity adhesive requirements.

Microstructure Evolution and Online Thermal Resistance of Ag Sintered SiC/DBA Power Module During Power Cycling

With the increasing power and miniaturization of power electronics, the power cycling reliability and thermal management of power modules have become increasingly crucial. To address this issue, our Lab. has developed a novel instrument that allows simultaneous power cycling and real-time thermal resistance measurement. Utilizing this specific instrument, we investigated the microstructural evolution of the die attachment layer during power cycling and monitored the real-time thermal resistance of the SiC-TEG (Silicon Carbide-Thermal Engineering Group) heater chip/sintered Ag/DBA (Directed Bonded Aluminum with ceramic core of Si3N4) structure. Additionally, strategies to improve the degradation of the microstructure were proposed. The results indicate that after 10000 power cycles, numerous cracks were observed in the sintered Ag layer. However, the addition of 5 wt. % A1 suppressed the generation of cracks significantly. The addition of A1 particles has little effect on the transient thermal resistance during power cycling.

Development of Dicing Die Attach Film (DDAF) for Small Dies

In recent years, the demand for ever smaller dies including Micro Electro-Mechanical System (MEMS) and sensors is dramatically increasing. Technologies such as automated driving technology are taking off and market pressures to reduce package size and increase the performance in mobile devices are increasing. DDAF increasingly is being utilized in these applications to bond dies to substrates and other dies. DDAF can be used both in the dicing and the die bonding process replacing the need for two separate materials to dice and bond dies. It is composed of DAF (Die Attach Film) and base material, and the DAF layer is what bonds small dies to substrates and other dies. Conventional DDAF however is susceptible to Transfer Failure (TF) with smaller die sizes. It is a failure mode in which the DAF layer peels off from the backside of the die during the die picking up (PU) process. There are multiple root causes for this issue; small dies have small DAF attachment area and smooth die backsides for increased die strength results in an inability of the DAF to anchor itself to the die. However, package reliability was decreased due to the material’s inability to embed itself on to the substrate. Effect factors for suppression of TF with high substrate embedding were explored. To explore these factors a right-angle tear strength method was implemented. Upon analysis of the data a new parameter for the suppression of TF was discovered. This parameter showed a strong correlation to TF. A new DDAF was developed that mitigates TF during PU proess.

Polyphenylene oxide/boron nitride–alumina hybrid composites with high thermal conductivity, low thermal expansion and ultralow dielectric loss

AbstractTraditional integrated circuit (IC) packaging materials and printed circuit board substrate materials suffer from several limitations including low thermal conductivity, high coefficient of thermal expansion (CTE), and poor dielectric properties. Although significant efforts have been made to enhance these properties, achieving a single composite system with simultaneous high thermal conductivity, extremely low CTE, and dielectric loss remains a formidable task. In this study, we propose a hybrid polymer composite system that addresses these challenges. Our approach involves utilizing a thermosetting polyphenylene oxide (PPO) as the resin matrix, while incorporating boron nitride (BN) sheets with high thermal conductivity and alumina (Al2O3) spheres with favorable fluidity as fillers. To optimize the composite properties, the filler surfaces are modified using dopamine and silane coupling agents, ensuring proper interface control. The composites exhibit significant improvements in thermal conductivity, reduced dielectric loss and CTE, while maintaining excellent processibility. Specifically, with a composition of 25 vol% BN and 25 vol% Al2O3, the thermal conductivity of the composite reaches 2.18 W·m−1 K−1, surpassing neat PPO resin by a factor of 10.9. Simultaneously, the CTE decreases from 2.27% to 1.18% between 50 and 260°C, and the dielectric loss reduces from 0.0024 to 0.0011 at 10 GHz, as compared to neat PPO resin.Highlights The reported novel hybrid composite offers a promising solution to the limitations of traditional IC packaging materials. The reported hybrid composite exhibits significantly improved thermal conductivity, ultralow dielectric loss, and reduced coefficient of thermal expansion, while maintaining excellent processibility. The thermal conductivity of the composites reaches 2.18 W·m−1 K−1, surpassing that of the neat resin by a factor of 10.9, meanwhile the dielectric loss is as low as 0.0011 at 10 GHz, which is extremely difficult to achieve simultaneously for thermosetting polymer composites. Synergetic effects were realized with the hybridization of fillers with different dimensionality, and proper filler surface modification.

Influence of the IC power supply and decoupling capacitor arrangement on the electromagnetic emission

With the advancing development of integrated circuits (ICs), more and more complex functions and higher performance levels can nowadays directly be integrated into a single IC package. In this context, the issue of electromagnetic compatibility (EMC) is becoming more critical, as the higher the integration density, the higher the electromagnetic emissions tend to be. In this paper, an EMC test IC is used to investigate the influence of different power supply pinouts (arrangement of VDD and GND pins in center and corner configuration) on the electromagnetic emission of the IC. This is done on the basis of the surface-scanning technique described in the IEC 61967‑3 standard for characterizing the magnetic near field at the surface of the IC package, and on the basis of the 150 Ohm measurement method described in IEC 61967‑4 for determining the conducted interference emissions at the power supply pinout of the IC. Both measurement methods show a significant difference in electromagnetic emissions due to the dependence on the arrangement of the power supply pinouts. These results highlight the importance of careful power supply design in the development of electromagnetically compatible ICs.

ELECTRON-BEAM SINTERING OF ZIRCONIUM DIOXIDE/TITANIUM CERAMICS FOR MICROELECTRONICS PRODUCTS

Zirconium dioxide (ZrO<sub>2</sub>) has excellent physical, chemical, and mechanical properties. These properties make it an excellent material for composite ceramics. High values of dielectric permittivity, mechanical resistance, and high radiation resistance allow it to be used to protect integrated circuits (ICs) from external influences. In this study, we fabricated ZrO<sub>2</sub>/titanium (Ti) ceramic composites by employing electron-beam sintering and a forevacuum-pressure plasma-cathode electron-beam source. We used a scanning electron microscopy method to study the properties of the ceramics after sintering. The results obtained showed that with an increase in the sintering temperature up to 1700°C, the Ti content in the near-surface layer of the composite decreased to almost 0. The depth of the region with low metal component content also increased with an increase in the sintering temperature and reached 2 mm in 3-mm-thick samples. This method can be used in the production of composite materials used in IC packaging.