Integrated Circuit Packaging Research Articles

Characterization of Multiple Commercial Sintered-silver Pastes as Die Attachment for Power Electronics Packaging: Materials, Processing, and Properties

Characterization of Multiple Commercial Sintered-silver Pastes as Die Attachment for Power Electronics Packaging: Materials, Processing, and Properties

Effect of Effective Curing Shrinkage of EMC on Strip Warpage During IC Encapsulation Process

Effect of Effective Curing Shrinkage of EMC on Strip Warpage During IC Encapsulation Process

Synthesis of Cobalt Particles and Investigation of Their Electromagnetic Wave Absorption Characteristics.

As the integration technology for integrated circuit (IC) packaging continues to advance, the issue of electromagnetic interference in IC packaging becomes increasingly prominent. Magnetic materials, acknowledged for their superior electromagnetic absorption capabilities, play a pivotal role in mitigating electromagnetic interference problems. In this study, we employed a liquid-phase reduction method. We prepared three types of cobalt (Co) particles with distinct morphologies. Through variations in the synthesis process conditions, we were able to control the aspect ratio of protrusions on the surface of the Co particles. It was found that the sword-like Co particles exhibit superior electromagnetic wave absorption capabilities, showing a reflection loss value of up to -50.96 dB. Notably, when the coating thickness is only 1.6 mm, the effective absorption bandwidth is extended up to 7.6 GHz. The spatially expansive sword-like Co particles, with their unique structure featuring dipole polarization and interfacial polarization, demonstrated enhanced dielectric and magnetic loss capabilities, concurrently showcasing superior impedance-matching performance.

Monomer ratio‐controlled polyimides with enhanced dielectric properties and thermal stabilities through crosslinking network

AbstractPolyimides (PI) are considered as one of the most used materials for flexible printed circuit board substrates because of their excellent thermal stabilities, outstanding mechanical properties, and great dielectric properties. Dielectric constants (Dk) of common commercial PIs, however, are still above 3.0 (at 10 GHz), which is still substandard for high‐frequency applications. In this study, we develop thermally stable PIs with enhanced dielectric properties by structural design and crosslinking. Stiff aromatic 2,2′‐bis(trifluoromethyl)benzidine (TFMB) and soft aliphatic dimer diamines (DDA, priamine), including priamine 1074 (DDA‐1) and priamine 1071 (DDA‐2), are used as the diamines, and cyclobutanetetracarboxylic dianhydride (CBDA) is used as the dianhydride. By adjusting the ratio of the diamines, a series of PIs (PI‐1–PI‐5) with high thermal stabilities and low‐Dk values are synthesized. Among these PIs, PI‐4 synthesized by diamines with the ratio of TFMB:DDA‐1:DDA‐2 = 85:10:5, possesses relatively good performances. Therefore, PI‐4 is further chosen to be thermally crosslinked. By changing the contents of the crosslinker, triallyl isocyanurate (TAIC), crosslinked PIs (CPIs) are synthesized. The resulting CPIs have a significant improvement in thermal properties, dielectric properties, and mechanical strengths. Especially, for the CPI‐4‐30, in which 30% of TAIC is used, the glass transition temperature (Tg) increases by 20°C, the Dk decreases from 2.62 to 2.41, and the ultimate tensile strength boosts from 91.65 to 115.16 MPa. The CPIs with low Dk and high Tg values may have great potential as substrate materials for broad applications, such as microelectronics and integrated circuit packages.

Driving Adoption of Advanced IC Packaging in Automotive Applications

For years automotive semiconductors, have been governed by small, low power Integrated Circuits (ICs) purpose built for specific functions. These Microcontroller Units (MCUs), deployed on the edge of the compute topology are typically low-power, low-performance parts. Built on legacy nodes (130nm+) on well-established packaging technology (often wirebond die on QFN-style packages), they demonstrated incremental improvements from a silicon and packaging perspective. With the adoption of software defined vehicles (SDV), the evolution of advanced driver assist systems (ADAS), and feature rich in-vehicle infotainment (IVI), the per vehicle compute power has grown exponentially per vehicle, colloquially, known as “data centers on wheels”. With this growth has come the need to adopt newer packaging techniques to improve system latency, bandwidth, compute power, and IP integration and reducing system footprint via 3D stacking – all fabricated on leading edge nodes. Advanced packaging has seen tremendous growth and adoption in the data center and client ecosystems – the next hurdle is addressing the safety and reliability focused requirements of automotives; extended useful lifespan of 10yrs+, and weathering harsher environmental conditions of thermal extremes, vibration, and EMC, and mixed IP integration. This talk will address the areas of focus for adopting heterogenous integration and advanced automotive packaging for automotives such as, qualification and formulation of materials to minimize traditional packaging yield concerns, introduction of new thermal interface materials aligned with new liquid cooled ECUs and testing to ensure zero defects across chiplets and memory; with broader test coverage and the adoption of Known Good Die (KGD). Additionally, the talk will cover the importance of driving industry standardization regarding die-to-die communication protocols, form factors, power delivery, system integration, and qualifying/enveloping new failure modes from the current baseline AEC-Q100 requirements brought on by various 2.5D and 3D packaging.

Advanced Thermal Interface Materials: Assembly and Integration for System in Package

Power dissipation is perhaps the greatest challenge facing modern electron devices. It has limited the performance of Si integrated circuits for nearly two decades, and is also limiting the performance of (high-power) GaN discrete devices. As such, many information technologies (ITs) have an urgent need for power dissipation solutions at the hardware level. The most feasible solution is via the device packaging, since self-heating of the device is deeply rooted in fundamental aspects of electron transport in imperfect semiconductors at normal temperatures. This packaging solution often occurs at the die attachment, whereby a thermal interface material (TIM) couples the device to the board. The interface/bulk thermal conductivity of this TIM determines the temperature rise of the device at a given operating power. Today, most TIMs rely on the thermal conductivity of metals, and are rapidly becoming a bottleneck for power dissipation in advanced ITs. This talk will discuss the limitations of metallic TIMs, and integration/characterization challenges for new materials that may extend the performance scaling of high-power devices.

Size effect on thermal transport performance of inserted Cu/Cu3Sn bilayer

Cu-Sn bonding is widely used in integrated circuits packaging due to the excellent stability and electrical performance, whose thermal transport mechanism is essential to be understood. Here, the size effect on thermal transport performance of Cu/Cu3Sn bilayer inserted between the diamond/carbon nanotube interface was comprehensively investigated. The thermal conductivities of phonon component and electron component were studied by non-equilibrium molecular dynamics simulation and thermal-electrical analogy, respectively. The thermal-electrical analogy was verified to be a promising way to predict the size effect of electron thermal conductivity. In view of interfacial thermal resistance (RK) is determined by phonon-phonon resistance, electron-phonon resistance, and electron-interface resistance, these three components were researched separately. At atomic level, the phenomenon of cross-layer effect and structural disorder were elaborated to reveal the mechanism of phonon heat transfer. The electron effects on RK were also well incorporated, to make our prediction approaching to real-world metal-dielectric interfacial heat transfer. Based on the above results, the total thermal resistance of the inserted Cu/Cu3Sn bilayer was calculated in the last section, revealing the dominant role of RK in micro/nano scale bonding. This work provides a comprehensive understanding of the thermal transport performance of multilayer metal bonding.

Effect of Nanoscale in Situ Interface Welding on the Macroscale Thermal Conductivity of Insulating Epoxy Composites: A Multiscale Simulation Investigation.

Insulating thermally conductive polymer composites are in great demand in integrated-circuit packages, for efficient heat dissipation and to alleviative short-circuit risk. Herein, the continuous oriented hexagonal boron nitride (h-BN) frameworks (o-BN@SiC) were prepared via self-assembly and in situ chemical vapor infiltration (CVI) interface welding. The insulating o-BN@SiC/epoxy (o-BN@SiC/EP) composites exhibited enhanced thermal conductivity benefited from the CVI-SiC-welded BN-BN interface. Further, multiscale simulation, combining first-principles calculation, Monte Carlo simulation, and finite-element simulation, was performed to quantitatively reveal the effect of the welded BN-BN interface on the heat transfer of o-BN@SiC/EP composites. Phonon transmission in solders and phonon-phonon coupling of filler-solder interfaces enhanced the interfacial heat transfer between adjacent h-BN microplatelets, and the interfacial thermal resistance of the dominant BN-BN interface was decreased to only 3.83 nK·m2/W from 400 nK·m2/W, plunging by over 99%. This highly weakened interfacial thermal resistance greatly improved the heat transfer along thermal pathways and resulted in a 26% thermal conductivity enhancement of o-BN@SiC/EP composites, compared with physically contacted oriented h-BN/EP composites, at 15 vol % h-BN. This systematic multiscale simulation broke through the barrier of revealing the heat transfer mechanism of polymer composites from the nanoscale to the macroscale, which provided rational cognition about the effect of the interfacial thermal resistance between fillers on the thermal conductivity of polymer composites.

Integrated Circuit Packaging Recognition with Tilt Auto Adjustment using Deep Learning Approach

A deep-learning-based approach for recognizing integrated circuit (IC) packaging type is presented in this paper. The objective of this work is to design a deep-learning method that can recognize multiple types of packaging per detection, performing counting operations, and calculating the centre location of an IC with its tilting angle. The transfer learning from model You-Only-Look-Once (YOLO) v5 was chosen because it has been trained with the coco dataset and has a more reliable feature extraction system than the other models. In order to extract data from images, OpenCV was used, which allows the deep learning model to perform more efficient analysis of the input data. Apart from that, the principal component analysis (PCA) was used to estimate the angle of the IC in order to determine the rotation of each IC for the purpose of tilting adjustment. The developed model has an average confidence score of 85% and is capable of operating in a variety of conditions, as demonstrated by ANOVA analysis.

Low-Temperature Die Attachment by Pressureless Cu Sintering for Semiconductor Packaging

Low-Temperature Die Attachment by Pressureless Cu Sintering for Semiconductor Packaging

Reliability Improvement of 3.3 kV Full-SiC Power Modules for Power Cycling Tests With Sintered Copper Die Attach Technology

Reliability Improvement of 3.3 kV Full-SiC Power Modules for Power Cycling Tests With Sintered Copper Die Attach Technology

WIRELESS ENVIRONMENTAL QUALITY MONITORING SYSTEM

Advances in commercial compact integrated circuit technology have made it possible to integrate wireless transceivers, signal processing, and sensors in a single integrated circuit package. Such solutions provide a low-cost means of communication with the physical world and can have applications in areas as diverse as security, production management, research and environmental monitoring. We outline the challenges of system design for a distributed sensor network in which each node has a limited power source and communication channel. The nodes must establish a synchronous network with multiple hops, determine locations, and communicate for purposes such as relaying a signal and transmitting data to a server device. The confluence of low-cost wireless, computing, and sensors has created a new generation of smart devices. The use of tens and thousands of such devices in self-organizing networks has led to the creation of a new technology called wireless sensor networks. In this article, we will consider an example of the use of such a network based on the Bluetooth Low Energy (BLE) wireless data transfer protocol, which gave a serious impetus to the development of wireless sensors. Together with organic polymers, which are used as a sensor layer, it is possible to achieve high energy efficiency and selective sensitivity in monitoring. It is also worth noting the fast and cheap production of electronics based on organic polymers. Due to the semiconductor and flexible properties of organic semiconductor materials, flexible organic electronics has become the core of our technology. The field of organic electronics is entering a commercial phase. The appearance on the market of the first prototypes based on organic transistors made from solutions is intended to expand the existing presence in the market of organic electronic devices. We'll look at some of the key performance requirements for working devices. We will also look at some of the important advances in semiconductor design and device manufacturing technologies and discuss some of the technical challenges that are needed to optimize next generation products.

Reliability Improvement of Low-Temperature Sintered Nano-Silver as Die Attachment by Porosity Optimization

Reliability Improvement of Low-Temperature Sintered Nano-Silver as Die Attachment by Porosity Optimization

Study of heat transfer performance of miniature heat sink for integrated circuit packaging field

The miniature heat sink is an essential component in integrated circuit packaging, playing a vital role in ensuring the stable and reliable performance of integrated circuits. In this paper, we establish a simulation model of the heat transfer performance of a miniature heat sink with a square columnar array microstructure and study the effect of the dimensional parameters of the miniature heat sink on the heat transfer performance. Then, the mathematical equations between the heat source temperature and the dimensional parameters of the miniature heat sink are obtained based on the response surface method, and the dimensional parameters are optimized. Finally, wire electrical discharge machining (WEDM) was used to prepare miniature heat sinks and to test the heat transfer performance. The experimental results show that both the simulation model and the mathematical equations have high accuracy, and the heat source temperature of the miniature heat sink with column width, column distance, and column height of 364 μm, 331 μm, and 1500 μm, respectively, can be reduced to 101.8 °C, which is 93.5 °C lower than the heat source temperature of 195.3 °C without heat sink, and the temperature reduction reaches 47.9%. The miniature heat sink has a simple manufacturing process, low manufacturing cost, small overall size, and good heat transfer performance, which has a broad application prospect in the field of integrated circuit packaging.

Copper-Wire Stress Buffers for Extending Lifetime of Double-Sided Bidirectional SiC Modules

The mismatch of thermal expansion coefficients causes tremendous thermo-mechanical stress in die attachment of double-sided bi-directional modules (BMs), thus reducing the reliability of the module. The thermo-mechanical reliability of a double-sided power module is the most critical issue, which needs to be addressed. People proposed ways to improve the reliability by reducing the CTE mismatches using such as Moly spacer instead of copper or junction temperature rise using high conductive spacer. This work first proposed a composite buffer, namely copper-wire-spacer (CWS), with low elastic modulus, capable of reducing thermo-mechanical stress by >50%. The lifetime of the double-sided BM with the CWS buffer is 40.0% and 42.9% longer than that with the conventional solid copper buffer, and is only 6.67% and 6.25% shorter than that with the moly buffer under the thermal shocking tests and the power cycling tests, respectively. The novel method of reducing the elastic modulus of the spacer could be a novel and good concept to reduce the thermo-mechanical stresses as well as improving the reliability of double-sided power modules. It can provide new guidance to design and packaging reliable double-sided power modules.

Generating Defective Epoxy Drop Images for Die Attachment in Integrated Circuit Manufacturing via Enhanced Loss Function CycleGAN

In integrated circuit manufacturing, defects in epoxy drops for die attachments are required to be identified during production. Modern identification techniques based on vision-based deep neural networks require the availability of a very large number of defect and non-defect epoxy drop images. In practice, however, very few defective epoxy drop images are available. This paper presents a generative adversarial network solution to generate synthesized defective epoxy drop images as a data augmentation approach so that vision-based deep neural networks can be trained or tested using such images. More specifically, the so-called CycleGAN variation of the generative adversarial network is used by enhancing its cycle consistency loss function with two other loss functions consisting of learned perceptual image patch similarity (LPIPS) and a structural similarity index metric (SSIM). The results obtained indicate that when using the enhanced loss function, the quality of synthesized defective epoxy drop images are improved by 59%, 12%, and 131% for the metrics of the peak signal-to-noise ratio (PSNR), universal image quality index (UQI), and visual information fidelity (VIF), respectively, compared to the CycleGAN standard loss function. A typical image classifier is used to show the improvement in the identification outcome when using the synthesized images generated by the developed data augmentation approach.

Prevention of Cu Electrolytic Migration Defects on RDL by a Cu-Selective Passivation to Enhance Reliability

Copper (Cu) is the metal of choice for the redistribution layer (RDL) to facilitate fast I/O communication in an integrated circuit (IC). Cu can electrochemically migrate (ECM) between the array of electrodes under bias, electrolyte, and moisture. IC packages fail miserably when exposed to various ion impurities and moisture. Copper at the anode dissolves to form Cu+1, +2 ions. As the anodic dissolution continues, the concentration of copper ion increases. These anions deposit on cathode leading to Cu dendrite formation. To achieve the near zero ppb defectivity goal, elimination of (ECM) defects in packaged devices is critical. This work discusses development of a novel Cu-selective passivation and a method to accelerate reliability testing. A hydrophobic passivation with minimum stress to the IC package is proposed in this work. The new passivation coating is thermally stable, strongly adheres to Cu, corrosion resistant, low cost and shows good potential to prevent ECM defects. The coated packaged devices were tested by an accelerated PEG drop test (PDT) to explore its ECM prevention capabilities.

Development of all new structure of Dicing Die Attach Film (DDAF) for Stealth Dicing and Cool Expansion processes

Mobile devices, including smart phones and tablets, are increasing in complexity and require ever greater amounts of memory storage. In the past the challenge of higher memory densities and increase functionality has been met through miniaturization of device features, but as we reach the physical limits of feature size, packaging is being relied on more and more to achieve the necessary higher densities in memory and additional device functionality. Thin dies reduce overall package height, however, to achieve high memory densities in low profile packages the die attach material must have an even, thin bond line thickness. DAF (Die Attach Film) is an excellent solution. LINTEC developed an all new DDAF (Dicing Die Attach Film) with thinner DAF for CE (Cool Expansion) process. Conventional tape has a large area of exposed DAF surface which creates the risk of wafer and / or equipment contamination if DAF flies off during the CE process. We developed an all-new tape structure which is compatible with the SD (Stealth Dicing) and CE processes. The structure consists of DAF, IB (Intermediate Basefilm), and dicing tape. The diameter of the DAF and IB is close to the wafer diameter size to significantly reduce the risk of DAF separation and ejection during CE. We considered IB to improve DAF separation and it was found that a thinner IB layer is a good approach to separate DAF effectively. We can adjust adhesion between the DAF and the IB by changing the material properties of the IB, as an effective means to control die-fly and pick-up.

Metal Oxide Removal Using Atmospheric Pressure Plasma Technology for Electronic Applications

Copper is one of the most commonly used metals in the electronics industry. For example, it is extensively used as a lead frame material in integrated circuit packaging due to its superior thermal and electrical conductivity and low production cost. However, the formation of a native oxide on the surface along with the presence of organic contaminants hinder wire bond strength. The work presented here will focus on a novel approach to remove copper and other oxide layers using a nitrogen/hydrogen (95%/5%) gas plasma chemistry that does not require a vacuum environment. The processes are run at temperature conditions lower than 200°C, and at speed up to 150 mm/s which make the technology attractive for industrial upscaling. Results from the elemental analysis using scanning electron microscopy (EDS-SEM) of the plasma-treated versus as-received copper surfaces will be presented. Also, a brief analysis of the gas plasma-surface interactions, process parameters leading to oxide reduction of various metals (Cu, Sn) and equipment details will be discussed. Aside from improving wire bond strength to lead frames and pads, plasmas can be used to improve die attachment to various metal solder materials for flip chip and other electronic applications.

A Detection method of electromagnetic analysis attacks based on change in amplitude of noise around integrated circuits

Electromagnetic analysis (EMA) attacks are a type of side-channel attacks that can be performed without opening or modifying a cryptographic module. In this study, we propose a detection method for the measurement of side-channel information, which is performed at the preliminary stage of the analysis of the target device as a countermeasure against EMA attacks performed near integrated circuits (ICs) with cryptographic modules. The presence of an electromagnetic (EM) field probe is detected by analyzing the sampling background noise around the IC using an analog-to-digital converter (ADC) inside the IC and by observing any changes in the EM environment. The proposed method can effectively detect a probe placed 5 cm from the IC package.