Defects In Integrated Circuits Research Articles

A cost-effective repair scheme for clustered TSV defects in 3D ICs

The current industry trend favors TSV (Through-Silicon-Via) based 3D ICs (Three-dimensional Integrated-Circuits) due to their several benefits. However, the complex manufacturing process emanates defects in TSVs. At the same time, clustered nature of TSV defects increases the probability of multiple defective neighbors TSVs. Therefore, reliability is one of the significant issues in the industry adoption of 3D integration based on TSVs. The repair solution of employing spare TSVs is an acceptable solution to enhance reliability. However, this solution incurs a significant amount of overheads. This study presents a cost-effective repair architecture to address the clustered TSV defects by organizing the neighbor TSVs. The proposed scheme secures a high repair rate for densely clustered defects. Besides, the proposed scheme reduces the significant area overhead compared to the existing TSV redundancy architectures.

Application of Artificial Intelligence in Integrated Circuits

Integrated circuit and artificial intelligence technology are inseparable. Artificial intelligence technology depends on the learning ability and computing ability of computers and other machines. In this process, integrated circuits provide hardware support for the operation of artificial intelligence algorithms. For a long time, the application research of artificial intelligence technology in the field of integrated circuit mainly focuses on circuit fault analysis and artificial intelligence chips. Especially in recent years, due to the rapid development of technology, the combination of the two has become more closely, and more scientists and researchers have invested in the interdisciplinary research of the two disciplines. In this paper, the application of artificial intelligence technology in the field of integrated circuits is explored, that is, its applications in the three aspects of chip, integrated circuit fault diagnosis and circuit design optimization is discussed, and the relationship between artificial intelligence technology and integrated circuit is reflected. Finally, it is concluded that the cross research and application of integrated circuit and artificial intelligence technology will have an important impact on the level of science and technology and the level of human social life.

Preliminary Study on the Model of Thermal Laser Stimulation for Defect Localization in Integrated Circuits

Thermal Laser Stimulation (TLS) is an efficient technology for integrated circuit defect localization in Failure Analysis (FA) laboratories. It contains Optical Beam-Induced Resistance Change (OBIRCH), Thermally-Induced Voltage Alteration (TIVA), and Seebeck Effect Imaging (SEI). These techniques respectively use the principle of laser-induced resistance change and the Seebeck effect. In this paper, a comprehensive model of TLS technology is proposed. Firstly, the model presents an analytical expression of the temperature variation in Integrated Circuits (IC) after laser irradiation, which quantificationally shows the positive correlation with laser power and the negative correlation with scanning velocity. Secondly, the model describes the opposite influence of laser-induced resistance change and the Seebeck effect in the device. Finally, the relationship between the current variation measured in the experiment and other parameters, especially the voltage bias, is well explained by the model. The comprehensive model provides theoretical guidance for the efficient and accurate defect localization of TLS technology.

Convolutional neural network model based on terahertz imaging for integrated circuit defect detections.

Detection of integrated circuit (IC) defects is vital in IC manufacturing. Traditional defect detection methods have relied on scanning electron microscopy and X-ray imaging techniques that are time consuming and destructive. Hence, in this paper we considered terahertz imaging as a label-free and nondestructive alternative. This study aimed to use a convolutional neural network model (CNN) to improve the performance of the terahertz imaging IC detection system. First, we constructed a terahertz imaging IC dataset and analyzed it. Subsequently, a new CNN structure was proposed based on the VGG16 network. Finally, it was optimized based on its structure and dropout rate. The method proposed above can improve IC defects detection accuracy of THz imaging. Most significantly, this work will promote the application of terahertz imaging in practice and provide a foundation to further research in relevant fields.

Automatic localization of signal sources in photon emission images for integrated circuit analysis

Defects localization is a key step in failure analysis of highly scaled complementary oxide semiconductor integrated circuits (ICs). It gives prior information on VLSI circuits and allows the designers to improve their diagnostic. Light emission techniques are efficient to localize defects in modern ICs. The identification of the emission spots is an essential step of the process because it shows where is located the electrical activity in the chip. Due to scaling, more and more emission nodes are located within the acquisition area so that large variations of emission intensity can exist. Thresholding techniques have been implemented, but they fail to provide an exhaustive localization. To overcome this problem, we introduce in this paper an automatic unsupervised process. It is based on a combination of median filtering, mathematical morphology and local maxima research. This new approach is evaluated and tested on 20 photon emission images (real and simulated). The final result is compared to an expert evaluation, and the detection quality is quantified.

In situ high-resolution thermal microscopy on integrated circuits

The miniaturization of metal tracks in integrated circuits (ICs) can cause abnormal heat dissipation, resulting in electrostatic discharge, overvoltage breakdown, and other unwanted issues. Unfortunately, locating areas of abnormal heat dissipation is limited either by the spatial resolution or imaging acquisition speed of current thermal analytical techniques. A rapid, non-contact approach to the thermal imaging of ICs with sub-μm resolution could help to alleviate this issue. In this work, based on the intensity of the temperature-dependent two-photon fluorescence (TPF) of Rhodamine 6G (R6G) material, we developed a novel fast and non-invasive thermal microscopy with a sub-μm resolution. Its application to the location of hotspots that may evolve into thermally induced defects in ICs was also demonstrated. To the best of our knowledge, this is the first study to present high-resolution 2D thermal microscopic images of ICs, showing the generation, propagation, and distribution of heat during its operation. According to the demonstrated results, this scheme has considerable potential for future in situ hotspot analysis during the optimization stage of IC development.

Microscopy image fusion algorithm based on saliency analysis and adaptive m-pulse-coupled neural network in non-subsampled contourlet transform domain

Microscopy image fusion, as a new item in related research field, has been extensively used in integrated-circuit defect detection and intaglio-plate-microstructure observation. In this article, a ...

Fault Signal Detection System of Large Scale Integrated Circuit Based on Single Chip Microcomputer

In the process of fault signal detection of large-scale integrated circuit, the fault signal detection can improve the working performance of large-scale integrated circuit. The traditional detection system is simple, time-consuming, and the error is large, the fault signal detection haslow accuracy. In view of this situation, a new design method of large scale integrated circuit fault signal detection system is proposed based on single chip microcomputer. S3C2410 is taken as hardware design basis, and the signal sensor is used, the software algorithm uses three B spline wavelet transform for ORB wave detection method. The detection is completed.The experiment experimental results show that the system can improve the detection accuracy greatly, and effectively improve the work efficiency.

Methodology and Equipments for Analog Circuit Parametric Faults Diagnosis Based on Matrix Eigenvalues

A method and corresponding equipments for analog circuit parametric faults diagnosis based on matrix eigenvalues are presented in this paper. The proposed method organizes the discrete samples of response signals of the circuits under test (CUT) into a square matrix and calculates out the maximal and minimal eigenvalues of the square matrix. According to the one-to-one correspondence relationship between the matrix elements and fault cases, fault detection and fault location are achieved by using the maximal and minimal eigenvalues as fault signatures. Two experimental results show that the proposed method has better fault coverage, higher computational efficiency and needs fewer test points than the other state-of-the-art methods. Without the necessary of node-voltage equation or internal structure analysis, solely, depending on the analysis of the output response of CUT to achieve the fault diagnosis, the presented method is particularly suitable for the analog integrated circuit fault diagnosis, and can be extended to solve the fault diagnosis for superconductor digital circuits with finite accessible nodes.

On-Chip Delay Measurement Based Response Analysis for Timing Characterization

We present techniques for response analysis for timing characterization, i.e., delay test and debug of Integrated Circuits (ICs), using on-chip delay measurement of critical paths of the IC. Delay fault are a major source of failure in modern ICs designed in Deep Sub-micron technologies, making it imperative to perform delay fault testing on such ICs. Delay fault testing schemes should enable detection of gross as well as small delay faults in such ICs to be efficient. Additionally there is a need for performing efficient and systematic silicon debug for timing related failures. The timing characterization techniques presented in this paper overcome the observability limitations of existing timing characterization schemes in achieving the aforementioned goals, thus enabling quick and efficient timing characterization of DSM ICs. Additionally the schemes have low hardware overhead and are robust in face of process variations.

Defect detection of IC wafer based on two-dimension wavelet transform

Defect detection of integrated circuit (IC) wafer based on two-dimension wavelet transform (2-D DWT) is presented in this paper. By utilizing the characteristics many of the same chips in a wafer, three images with defects located in the same position and different chips are obtained. The defect images contain the standard image without any defects. 2-D DWT presented in the paper can extract the standard image from the three defect images. The algorithm complexity of the method is close to that of 2-D DWT. After obtaining the standard image, the speed and accuracy of defects detection can be greatly enhanced using the detection method presented in the paper. Using the image gray-scale matching technology, impact of illumination on IC defect detection is solved. Experiments demonstrate that 2-D DWT is fast and accurate to defects detection in an IC image, and the method has high robustness for illumination.

Defect Detection of IC Wafer Based on Spectral Subtraction

In this paper, spectral subtraction is successfully applied to image processing and to detect defects in the integrated circuit (IC) image. By utilizing the characteristics of many of the same chips in a wafer, three images with defects located in the same position and different chips are obtained. The defect images contain the spectrum of standard image without any defects. Spectral subtraction presented in the paper can extract the standard image from the three defect images. The algorithm complexity of spectral subtraction detecting defects is close to that of Fourier transform. After obtaining the standard image, the speed and accuracy of defects detection can be greatly enhanced using the detection method presented in the paper. Using the image gray-scale matching technology, impact of illumination on IC defect detection is solved. Experiments demonstrate that spectral subtraction is fast and accurate to defect detection in an IC image, and the method has high robustness for illumination.

Design considerations for refractive solid immersion lens: Application to subsurface integrated circuit fault localization using laser induced techniques

With fast scaling and advancement of integrated circuit (IC) technology, circuitries have become smaller and denser. New materials and more sophisticated designs have evolved. These changes reduced the effectiveness of conventional laser induced fault localization techniques. Since IC fault localization is the most critical step in failure analysis, there are strong motivations to improve both spatial resolution and sensitivity of such systems to meet the new challenges from advanced technology. Refractive solid immersion lens (RSIL) is well known to enhance the laser spot size which directly affects resolution and sensitivity in back side fault localizations. In practice, it is difficult to operate RSIL at the ideal configurations to obtain the smallest spot resolution. It is necessary to understand the resolution performance at the other design focal planes. Besides resolution, there are also other factors that affect sensitivity in a RSIL enhanced system. This paper identifies and characterizes key RSIL design parameters to optimize RSIL performance on laser induced techniques. We report that the most efficient conditions are achieved close to aplanatic RSIL design to within 20-25 microm (for a 1 mm diameter lens), and the backing objective should be the minimum numerical aperture required for optimum resolution performance. The size of the mechanical clear aperture opening should be large enough (>80%) to exploit the advantage of aplanatic RSIL. RSIL is developed on a laser scanning optical microscope in this work, and a resolution of 0.3 microm (for a wavelength of 1340 nm) was achieved over a range of operating conditions. A quantitative resolution of 0.25 microm is achieved and a pitch structure of 0.4 microm is easily resolvable. Close to 15 times enhancement in laser induced signal is obtained.

Micromachining of semiconductor by femtosecond laser for integrated circuit defect analysis

The latest International Technology Roadmap for Semiconductors (ITRS) has highlighted the detection and analysis of defects in Integrated Circuits (IC) as a major challenge faced by the semiconductor industry. Advanced tools used today for defect cross sectioning include dual beams (focused ion- and electron-beam technologies) with resolution down to the sub-Angstrom level. However ion milling an IC with a FIB is time consuming because of the need to open wide cavities in front of the cross-sections that need to be analyzed. Therefore the use of a femtosecond laser as a tool for direct material removal is discussed in this paper. Experiments were performed on IC structures to reveal the different layers of fabrication: selective or total ablation can occur depending on the laser energy density, without delamination of the layers. Different laser irradiation conditions like pressure (air, vacuum), polarization, beam shaping, and scanning parameters have been used to produce different types of cavities. The femtosecond laser engraving of silicon-based structures could be useful for cross-sectioning devices but also for other applications like direct-write lithography, photomask repair, maskless implantation or reverse engineering/restructuring.

High-resolution differential thermography of integrated circuits with optical feedback laser scanning microscopy

We demonstrate a noninvasive technique for generating differential thermal maps of semiconductor edifices in integrated circuits (IC) at diffraction-limited resolution. An inexpensive optical feedback laser-scanning microscope detects changes in the optical beam-induced currents (OBIC) that are produced in the active layer in response to variations in the IC package temperature. The OBIC yield of a semiconductor normally increases with temperature. A differential thermal map derived from the OBIC output variations, shows locations of high thermal activity in the active layer including anomalous regions where the OBIC outputs decrease with increasing temperature. Anomalous regions are loci of accumulating semiconductor electrical resistance that are highly susceptible to device failure. They provide the best jump-off points for efficient and accurate IC fault analysis procedure.

Fault simulation and modelling of microelectromechanical systems

High-reliability and safety-critical markets for microelectromechanical systems are driving new proposals for the integration of efficient built-in test and monitoring functions. The realisation of this technology will require support tools and validation methodologies including fault simulation and testability analysis and full closed-loop simulation techniques to ensure cost and quality targets. This article proposes methods to extend the capabilities of mixed signal and analogue integrated circuit fault simulation techniques to MEMS by including failure mode and effect analysis data and using behavioural modelling techniques compatible with electrical simulators.

Analysis of integrated circuit fault data using generalized linear models

Fault data for integrated circuits manufactured on silicon wafers are usually presented using wafer maps to indicate the spatial distribution of defects. This paper shows how this type of spatial data can be analyzed under the framework of generalized linear models. This provides a systematic method for monitoring the quality of a manufacturing process, and identifying fault sources with assignable causes that may possibly be eliminated with process improvement as a result. We consider models that account for different spatial patterns and, in particular, the observed phenomenon that the faults are distributed non-uniformly across the wafer. Furthermore, we demonstrate how designed experiments can be used in optimizing the setting of important process parameters. Copyright © 2000 John Wiley & Sons, Ltd.

Analysis of integrated circuit fault data using generalized linear models

Analysis of integrated circuit fault data using generalized linear models

Defect tolerance in VLSI circuits: techniques and yield analysis

Current very-large-scale-integration (VLSI) technology allows the manufacture of large-area integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yield-reducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of yield-enhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Design-stage yield-enhancement techniques are aimed at making the integrated circuit defect tolerant, i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defect-tolerant chips must rely on accurate yield projections. This paper reviews the currently used statistical yield-prediction models and their application to defect-tolerant designs. We then provide a detailed survey of various yield-enhancement techniques and illustrate their use by describing the design of several representative defect-tolerant VLSI circuits.

The nuclear microprobe: a unique instrument

There are several features characterising high-energy ion interactions with matter which enables techniques which utilise the high-energy ion beam to have unique or advantageous characteristics. (i) The lack of primary particle bremsstrahlung enables Particle Induced X-ray Emission (PIXE) to be carried out with very little X-ray background, and therefore correspondingly high analytical sensitivity. (ii) The ion beam can penetrate many microns beneath the surface of the specimen with relatively little scattering, and therefore information on structures beneath the surface can be investigated at relatively high spatial resolution. (iii) The ion beam has a well defined depth in the sample, the depth depending on its energy, and this allows more complex three-dimensional structures of better depth definition to be micromachined compared with its X-ray counterpart LIGA. Illustrating these three important features are descriptions of recent work carried out on the elemental analysis of single cells, determination of the annealing efficiency of phosphorous implanted diamond, multi-layer integrated circuit fault finding, and proton micromachining of high aspect ratio structures.