Analysis of integrated circuit fault data using generalized linear models

Abstract

Fault data for integrated circuits manufactured on silicon wafers are usually presented using wafer maps to indicate the spatial distribution of defects. This paper shows how this type of spatial data can be analyzed under the framework of generalized linear models. This provides a systematic method for monitoring the quality of a manufacturing process, and identifying fault sources with assignable causes that may possibly be eliminated with process improvement as a result. We consider models that account for different spatial patterns and, in particular, the observed phenomenon that the faults are distributed non-uniformly across the wafer. Furthermore, we demonstrate how designed experiments can be used in optimizing the setting of important process parameters. Copyright © 2000 John Wiley & Sons, Ltd.