Integral Nonlinearity Research Articles

An 18.39 fJ/Conversion-Step 1-MS/s 12-bit SAR ADC With Non-Binary Multiple-LSB-Redundant and Non-Integer-and-Split-Capacitor DAC

A low-power 12-bit successive approximation register (SAR) analog-to-digital converter (ADC) with split-capacitor, nonbinary-weighted, and multiple-least-significant-bit (LSB)-redundant capacitor digital-to-analog converters (CDACs) is proposed. The proposed SAR ADC with nonbinary-weighted and multiple-LSB-redundant CDACs has an optimal mechanism for correcting the bit error decisions due to noise and incomplete digital-to-analog converter (DAC) switching settling. To reduce the total capacitance, all capacitor values of the 12-bit DAC were divided by 16, and a parallel-series capacitor scheme was used to implement these noninteger capacitors. The 12-bit SAR ADC prototype was fabricated using 0.18-μm 1P6M complementary metal oxide semiconductor technology. The maximal differential nonlinearity and integral nonlinearity were measured as -0.4/0.54 and -0.81/0.89 LSB, respectively, where 1 LSB = 0.488 mV. The signal-to-noise-and-distortion ratio and effective number of bits were 69.51 dB and 11.25 bits, respectively, for the input frequency of 500 kHz and sampling rate of 1 MS/s. The proposed SAR ADC features an 18.39-fJ/conversion-step Figure-of-Merit (FoM) at the sampling rate of 1 MS/s.

Three-Step Cyclic Vernier TDC Using a Pulse-Shrinking Inverter-Assisted Residue Quantizer for Low-Complexity Resolution Enhancement

Herein, we present a cyclic Vernier time-to-digital converter (TDC) using a pulse-shrinking inverter-assisted residue quantizer (IRQ). Previous pulse-shrinking techniques suffer from a nonuniform shrink rate and time offset that slows the conversion and increases power consumption. The proposed pulse-shrinking IRQ reduces the time difference between residue signals instead of shrinking the pulse width. This approach achieves a high resolution with low power consumption and a high conversion rate. The critical tradeoff between resolution and dynamic range (DR) is addressed using a three-step cyclic conversion approach: coarse, fine, and residue quantization steps. The adverse effect of the oscillator startup time on linearity is analyzed, and a correction method is proposed using both on-chip circuit design and off-chip data processing. The proposed TDC is fabricated using a 180-nm CMOS process in a core area of 0.11 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The TDC can be configured into one of four resolution modes, 36, 64, 89, and 135 ps, at conversion rates of 0.82, 1.29, 1.47, and 1.86 MS/s, respectively. A wide DR of up to 179 ns is achieved. The linearity is well performed with a maximum integral nonlinearity (INL)/differential nonlinearity (DNL) of 0.4/0.73 LSB at a conversion rate of 1.86 MS/s. An effective number of bits, N <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">linear</sub> up to 9.88-bit, and a figure-of-merit (FoM) down to 0.31 pJ/conversion are achieved by consuming 0.55 mW.

A high-precision time-to-digital converter applied to CDC

This paper presents a high-precision CMOS time-to-digital converter (TDC) applied to a capacitance-to-digital converter (CDC). The time-to-digital converter in the capacitance-to-digital converter is used to measure the time interval between the charging time of the capacitor under test and the charging time of the internal reference capacitor. The time resolution of the TDC directly determines the capacitance resolution of the CDC. In order to improve the measurement resolution of TDC, a TDC structure based on phase-locked loop (PLL) is proposed. This paper first gives a capacitance-to-digital converter scheme, and then introduces the time-to-digital converter used in the scheme. The frequency multiplication technology of the phase-locked loop optimizes the integral nonlinearity (INL) of the interpolator and greatly improves the interpolation of the interpolation ratio. The TDC was realized in a 0.13-μm CMOS process, and the measurable time interval is 21.14μs. When the external reference clock is 200MHz, the resolution is 40.3ps and only 31 delay units are needed.

Merenje snage i energije vetra korišćenjem anemometra bez pokretnih delova

The paper deals with the application of a newly developed anemometer without moving parts. It is digitized and has built-in electronics that convert the vibrations of two aluminum fixed frames into two digital signals: one, which shows the strength (speed absolute value)) of the wind, and the other, which shows its direction. Earlier works have shown that the two-bit stochastic digital measurement method overcomes (eliminates) the problem of the offset of the analog adder. The authors of this paper apply this idea to the digital output of the sensor, where the role of the offset of the analog adder is taken over by the integral nonlinearity of the digital output of the anemometer. The first step in this direction is dithering digitally the sensor output. This principle is presented in detail, as well as a rough estimate of the accuracy gain in measuring wind energy.

An 8-Bit 1-GS/s Asynchronous Loop-Unrolled SAR-Flash ADC With Complementary Dynamic Amplifiers in 28-nm CMOS

An 8-bit 1-GS/s asynchronous loop-unrolled (LU) successive approximation register (SAR)-Flash hybrid analog-to-digital converter (ADC) with complementary dynamic amplifiers (CDAs) is presented. The proposed ADC is a combination of an asynchronous LU-SAR ADC and a reference-embedding 8 × interpolating flash (I-Flash) ADC to enhance the conversion speed. Operating the CDAs in a dual-edge manner makes it possible to achieve an 8-bit resolution with only four CDAs and one capacitive digital-to-analog converter (C-DAC), which improves the power and area efficiency as well as the input bandwidth. A prototype ADC implemented in a 28-nm CMOS process occupies a 0.002 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area. The measured differential non-linearity (DNL) and integral non-linearity (INL) after offset calibration is 0.59 and 0.82 LSB, respectively. With a 0.499-GHz input, the measured signal-to-noise and distortion ratio (SNDR) and the spurious-free dynamic range (SFDR) are 45.5 and 59.4 dB, respectively. The measured effective resolution bandwidth (ERBW) is above 3 GHz. The power consumption at 1-GS/s conversion is 2.55 mW with a supply voltage of 1.1 V, leading to a figure of merit (FoM) of 16.6 fJ/conversion-step.

Blumino: The First Fully Integrated Analog SiPM With On-Chip Time Conversion

Blumino is the first analog silicon photomultiplier with integrated amplifier, comparator and time-to-digital converter (TDC). The combination of a photodetector together with on-chip readout circuitry enables system-level advantages, such as internal parasitic reduction, compactness and simplicity. The analog silicon photomultiplier has a third output, called fast terminal (FT), in addition to the anode and cathode, which is used for timing measurements. The analog silicon photomultiplier presents excellent photon detection efficiency greater than 40% at 420 nm, making it suitable for positron-emission tomography. Measurement results of the TDC indicate a resolution of 128 ps least significant bit (LSB) with a differential nonlinearity and integral nonlinearity of -1/+5 LSB and -2.4/+0.9 LSB, respectively. The discriminator comprises two preamplifier stages followed by a complementary self-biased differential amplifier stage which is coupled to the analog silicon photomultiplier's FT through a decoupling capacitor. The sensor is also fully backward-compatible through the standard output which can be coupled to dedicated ASICs and standard readout integrated circuits. In addition to the electrical, radiation, and optical performance, the integration of a custom CMOS analog silicon photomultiplier process with standard CMOS process was investigated.

A 10-Bit Current Output DAC With Active Resistive Load Interpolation

This brief proposes a novel current output resistor string DAC architecture implemented for a 10-bit resolution. The DAC consists of a 6-bit coarse resistor string DAC followed by a 4-bit multi-input interpolation amplifier, and a voltage to current conversion stage. Use of a multi-input interpolation amplifier with shared resistive load provides accurate fine conversion with reduced resistor count. The current output DAC has high output impedance from the regulated current source architecture. The prototype was fabricated in a 0.18 μm CMOS process technology. The measured integral non-linearity (INL) and differential non-linearity are 0.5 LSB and 0.4 LSB, respectively. The chip consumes static power 0.54 mW at 1.8 V supply and occupies 0.042 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> area.

Design and implementation of 4 bit binary weighted current steering DAC

A compact current-mode Digital-to-Analog converter (DAC) suitable for biomedical application is repesented in this paper .The designed DAC is binary weighted in 180nm CMOS technology with 1.8V supply voltage. In this implementation, authors have focused on calculaton of Non linearity error say INL and DNL for 4 bit DAC having various type of switches: NMOS, PMOS and Transmission Gate. The implemented DAC uses lower area and power compared to unary architecture due to absence of digital decoders. The desired value of Integrated non linearity (INL) and Differential non linearity (DNL) for DAC for are within a range of +0.5LSB. Result obtained in this works for INL and DNL for the case DAC using Transmission Gate is +0.34LSB and +0.38 LSB respectively with 22mW power dissipation.

A 360-fs-Time-Resolution 7-bit Stochastic Time-to-Digital Converter With Linearity Calibration Using Dual Time Offset Arbiters in 65-nm CMOS

This article presents a 7-bit stochastic time-to-digital converter (STDC) with dual time offset arbiters that enables linearity calibration. The dual time offset arbiter with 1-bit mode selection effectively doubles time offsets available for time-to-digital conversion with minimal increase in hardware complexity. A genetic algorithm (GA)-based linearity calibration efficiently searches a huge search space to find the optimal time offset mode selection setting and a set of arbiters that lead to minimal integrated nonlinearity (INL). The combination of dual time offset arbiters and GA-based linearity calibration enables the proposed STDC to achieve ultrafine time resolution and a good linearity simultaneously. The proposed STDC also guarantees robust performance against on-die variation and gains good scalability with process technology as the linearity calibration is performed purely in the digital domain. A test chip prototype fabricated in a 65-nm CMOS technology demonstrates 360-fs time resolution with 0.75-LSB INL at 100 MS/s. The prototype achieves the effective time resolution of 630 fs, which is 1.5 times improvement compared with the prior arts.

A high energy-efficiency and low-area switching scheme for SAR ADCs

A high energy-efficiency and low-area switching method is proposed for the successive approximation register analog-to-digital converters. In the proposed scheme, the threshold voltage for comparison is derived from the charge sharing technique and using a voltage source connected to the bottom plates of the digital-to-analogue converter (DAC) capacitors. The switching method achieves an average DAC switching energy and DAC area reduction of 99.15% and 84.27%, respectively, with respect to the conventional method. The differential nonlinearity and integral nonlinearity of the proposed scheme are 0.1288 LSB and 0.1207 LSB, respectively. In addition, in the proposed method, the number of DAC switches is lower than the conventional and some other methods, which avoids further complicating the logic circuit as well as increasing wiring and area. Moreover, only one voltage source is used as a reference voltage, which makes us needless to have an extra voltage source that must be very accurate.

A 12-Bit 0.5–2.4-GHz 0.65°-Peak-INL Parasitic-Insensitive Digital-to-Phase Converter

A 12-bit 0.5–2.4-GHz parasitic-insensitive digital-to-phase converter (DPC) with high linearity is presented in this letter. A modified parasitic-insensitive charge-based (PICB) phase interpolator (PI) is proposed to avoid linearity degradation caused by parasitic effect. A novel PI cell with separated clock selecting logic is implemented to solve charge leakage and overcharging problem. The DPC is designed and fabricated in 40-nm CMOS technology, which occupies a chip area of 0.04 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and consumes 18.3 mW from a 1.3-V supply voltage. Operating in a frequency range from 0.5 to 2.4 GHz, the DPC demonstrates a peak integral nonlinearity (INL) of 0.65° and a peak differential nonlinearity (DNL) of 0.25°.

Multiple time-over-threshold readout electronics for fast timing and energy resolving in a SiPM-based positron annihilation lifetime spectrometer

Fast timing and energy resolving capabilities are crucial for a silicon-photomultiplier-based positron annihilation lifetime (SiPM-PAL) spectrometer. Time-over-threshold (ToT) offers an attractive method for combining timing and energy encoding with the advantage of simplicity in electronics implementation and SiPM readout. However, single ToT is not appropriate for a SiPM-PAL spectrometer because of its poor energy linearity and limited energy range. In this work, a multi-ToT readout circuit for a SiPM-PAL spectrometer is developed. Each readout channel uses only a pre-amplifier and a comparator for timing, three comparators for energy resolving, resistors, and capacitors. A simple pulse area estimation method using multi-ToT pulse widths and fixed threshold voltages for energy resolving is presented and evaluated. The energy performance and pulse area integral nonlinearity (INL) are investigated using 22Na, 60Co, and 137Cs γ sources with a SiPM-based scintillation detector. For pulse area spectra using the proposed method, multi-ToT (triple and dual threshold cases) resolves γ energies much better than does single ToT. Using triple-ToT, the pulse area linearity in INL in the energy range of 511–1333 keV is superior than 4.21%, which is at least 25% better than that with dual-ToT. Excellent coincidence resolving times of 161.5 ± 1.4 ps and 162.7 ± 1.3 ps in full width at half maximum are achieved using triple-ToT and dual-ToT, respectively, for 3 mm\\;×\\;3 mm\\;×\\;5 mm lutetium-fine-silicate scintillators. The quantitative energy and timing results show that the multi-ToT circuit is suitable for the readout electronics of a SiPM-PAL spectrometer.

A 5.2-Mpixel 88.4-dB DR 12-in CMOS X-Ray Detector With 16-bit Column-Parallel Continuous-Time Incremental ΔΣ ADCs

This article presents a 5.2-Mpixel, 12-in wafer-scale CMOS X-ray detector that consists of lithographically stitched 169 sub-chips. The detector employs a 3T pixel with a voltage-controlled storage capacitor to achieve both a low dark random noise (RN) and a large well capacity, and the pixel outputs are read out by column-parallel continuous-time (CT) incremental delta-sigma (ΔΣ) analog-to-digital converters (ADCs). The use of a CT incremental ΔΣ ADC enables high resolution and low energy consumption while securing uniformity and robustness over the 12-in wafer. This work is fabricated in a 1P4M 65-nm CMOS technology. The 16-bit ADC implemented within a 45-μm pitch achieves a differential nonlinearity (DNL) of +0.79/-0.65 LSB, an integral nonlinearity (INL) of +6.85/-6.15 LSB, and a peak signal-to-noise ratio (SNR) of 88.5 dB with a conversion time of 12.6 μs. This detector achieves a CFPN of 181 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , a dark RN of 267 μV <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , and a DR of 88.4 dB while consuming 3.9 W at 30 frames/s. Compared with the state of the arts, this work achieves 3× larger spatial resolution, 1.8× higher pixel rate, 1.9× higher energy-efficiency, and 17 dB higher DR, simultaneously.

A Highly Linear 10-Bit DAC of Data Driver IC Using Source Degeneration Load for Active Matrix Flat-Panel Displays

This brief proposes a highly linear digital-to-analog converter (DAC) of the data driver IC for active matrix flat-panel displays (AMFPDs). The proposed 10-bit two-stage DAC is realized with an upper 6-bit decoder and a lower 4-bit DAC-embedded amplifier. The decoder in the first stage selects two adjacent voltages from among the reference voltages of the R-string according to the upper 6-bit. The DAC-embedded amplifier in the second stage employs a source degeneration load to have the output current proportional to the input voltage, thus achieving the consistent transconductance of the input differential pairs, resulting in a high linearity. To verify the performance of the proposed DAC, a data driver IC with the proposed 10-bit DAC was fabricated using an 80 nm standard CMOS process with 8 V high-voltage devices. The measurement results show that the worst differential nonlinearity and integral nonlinearity are +0.26/-0.31 LSB and +0.57/-0.58 LSB, respectively. The measured worst inter-channel deviation of voltage outputs is 1.65 mV. Therefore, the proposed highly linear DAC is suitable for data driver ICs in high image quality AMFPD applications.

Fine resolution delay tuning method to improve the linearity of an unbalanced time‐to‐digital converter on a Xilinx FPGA

In this study, a method for fine adjustment of Xilinx field programmable gate array (FPGA) routing delays is proposed and applied to improve the linearity of an unbalanced multi-measurement time-to-digital converter (TDC). The delay control method increases load capacitances of interconnect points of switch matrices by small amounts using additional connections to unused interconnects in the FPGA fabric. The novel delay control method uses the tool command language (TCL) scripting feature available in the Xilinx Vivado tool to automatically add wires into a fully placed and routed design. A total of 61 additional wires were successfully and automatically added to reduce the differential and integral non-linearities of the target TDC from 0.51 and −0.54 LSB to 0.05 and 0.06 LSB, respectively (reduction factors of 10.2 and 9) for an LSB equal to 333 ps.

A 4-bit 36 GS/s ADC with 18 GHz Analog Bandwidth in 40 nm CMOS Process

This paper presents a 4-bit 36 GS/s analog-to-digital converter (ADC) employing eight time-interleaved (TI) flash sub-ADCs in 40 nm complementary metal-oxide-semiconductor (CMOS) process. A wideband front-end matching circuit based on a peaking inductor is designed to increase the analog input bandwidth to 18 GHz. A novel offset calibration that can achieve quick detection and accurate correction without affecting the speed of the comparator is proposed, guaranteeing the high-speed operation of the ADC. A clock distribution circuit based on CMOS and current mode logic (CML) is implemented in the proposed ADC, which not only maintains the speed and quality of the high-speed clock, but also reduces the overall power consumption. A timing mismatch calibration is integrated into the chip to achieve fast timing mismatch detection of the input signal which is bandlimited to the Nyquist frequency for the complete ADC system. The experimental results show that the differential nonlinearity (DNL) and integral nonlinearity (INL) are −0.28/+0.22 least significant bit (LSB) and −0.19/+0.16 LSB, respectively. The signal-to-noise-and-distortion ratio (SNDR) is above 22.5 dB and the spurious free dynamic range (SFDR) is better than 35 dB at 1.2 GHz. An SFDR above 24.5 dB and an SNDR above 18.6 dB across the entire Nyquist frequency can be achieved. With a die size of 2.96 mm * 1.8 mm, the ADC consumes 780 mW from the 0.9/1.2/1.8 V power supply.

Fixed Pattern Noise Reduction and Linearity Improvement in Time-Mode CMOS Image Sensors

In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.

Fractional-Order Integro-Differential Multivalued Problems with Fixed and Nonlocal Anti-Periodic Boundary Conditions

This paper studies a new class of fractional differential inclusions involving two Caputo fractional derivatives of different orders and a Riemann–Liouville type integral nonlinearity, supplemented with a combination of fixed and nonlocal (dual) anti-periodic boundary conditions. The existence results for the given problem are obtained for convex and non-convex cases of the multi-valued map by applying the standard tools of the fixed point theory. Examples illustrating the obtained results are presented.

A 0.5-V BLE Transceiver With a 1.9-mW RX Achieving −96.4-dBm Sensitivity and −27-dBm Tolerance for Intermodulation From Interferers at 6- and 12-MHz Offsets

This article presents a 0.5-V RF transceiver fully compliant with Bluetooth low energy (BLE) standards. The receiver (RX) fabricated in a 22-nm fully depleted silicon on insulator (FD-SOI) process achieves a sensitivity of -96.4 dBm, an intermodulation tolerance of -27 dBm for interferers at 6- and 12-MHz offsets, while consuming 1.9 mW. An RX-chain with a gain-programmable low-noise transconductance amplifier (LNTA) provides good linearity over a wide input power range. The LNTA changes amplifier topology according to the gain setting. It achieves a gain range of 41 dB and the IIP3 of -13 dBm at maximum gain. The proposed asynchronous SAR-ADC-based time-to-digital converter (TDC) for the all-digital phase-locked loop (ADPLL) is suitable for low-voltage operation and low-power consumption. It achieves a differential nonlinearity (DNL) of ±0.62 LSB and an integral nonlinearity (INL) of ±0.63 LSB.

A 32 × 32-Pixel CMOS Imager for Quantum Optics With Per-SPAD TDC, 19.48% Fill-Factor in a 44.64-μm Pitch Reaching 1-MHz Observation Rate

This article reports the design and characterization of a 32 $\times $ 32 single-photon avalanche diode (SPAD) time-resolved image sensor for quantum imaging applications fabricated in a 150-nm CMOS standard technology. A per-SPAD time-to-digital converter (TDC) records the spatial cross correlation functions of a flux of entangled photons. Each 44.64- $\mu \text{m}$ pixel with 19.48% fill-factor features a 210.2-ps resolution, 50-ns (8-bit) range TDC with 1.28-LSB differential and 1.92-LSB integral nonlinearity (DNL/INL). The sensor achieves an observation rate of up to 1 MHz through a current-based mechanism that avoids reading empty frames when the photon rates are low. A row-skipping mechanism detects the absence of SPAD activity in a row to increase the duty cycle. These two features require only three transistors in each pixel. The sensor functionality is demonstrated in a quantum imaging experiment that achieves super-resolution.