Abstract

In the paper, a digital clock stopping technique for gain and offset correction in time-mode analog-to-digital converters (ADCs) has been proposed. The technique is dedicated to imagers with massively parallel image acquisition working in the time mode where compensation of dark signal non-uniformity (DSNU) as well as photo-response non-uniformity (PRNU) is critical. Fixed pattern noise (FPN) reduction has been experimentally validated using 128-pixel CMOS imager. The reduction of the PRNU to about 0.5 LSB has been achieved. Linearity improvement technique has also been proposed, which allows for integral nonlinearity (INL) reduction to about 0.5 LSB. Measurements confirm the proposed approach.

Highlights

  • Parallel image acquisition in CMOS image sensors [1,2,3,4,5] is frequently based on time-to-digit analog-to-digital converters (ADCs) due to a relatively small silicon area and easy pixel integration

  • The paper presents the technique of clock stopping‐based gain and offset correction applied to time‐mode ADCs implemented in pixels of a CMOS imager chip

  • The technique was confirmed with measurements demonstrating a significant reduction of Fixed pattern noise (FPN) noise

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Summary

Introduction

Parallel image acquisition in CMOS image sensors [1,2,3,4,5] is frequently based on time-to-digit analog-to-digital converters (ADCs) due to a relatively small silicon area and easy pixel integration. An additional benefit is fully parallel analog-to-digital conversion, which makes global shutter implementation easy. ADC integration in the pixels resulted in low fill-factor. Due to the growing popularity of imagers implemented in 3-D technology [6,7,8,9], fill-factor is no more a significant limitation in the application of time-mode converters. The separation between the analog and digital domains makes imagers more robust to interference and allows for the use of optimal technology for analog and digital dies

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