Input Parasitic Capacitance Research Articles

A 382nVrms 100GΩ@50Hz Active Electrode for Dry-Electrode EEG Recording.

This article describes a low noise and ultra-high input impedance active electrode (AE) interface chip for dry-electrode EEG recording. To compensate the input parasitic capacitance and the ESD leakage, power/ground/ESD bootstrapping is proposed. This design integrates chopping stabilization technique to suppress flicker noise of the amplifier which has never been tackled in previous bootstrapped AE design. Both on-chip and off-chip input routing is active shielded to minimize wire parasitic. Fabricated in a 0.18μm CMOS process, the AE core occupies about 0.056mm2 and draws 17.95μA from a 1.8V supply. The proposed AE achieves 100GΩ input impedance at 50Hz and over 1GΩ at 1kHz with a low input-referred noise of 382nVrms integrated from 0.5Hz to 70Hz. This design is the first 100GΩ@50Hz input impedance chopper stabilized AE compared to the state-of-the-art. Dry-electrode EEG recording capability of the proposed AE are verified on three types of experiments including spontaneous α-wave, event related potential and steady-state visual evoked potential.

A low-noise, radiation-hardened charge-sensitive amplifier for Silicon carbide neutron detector

Silicon carbide(SiC) neutron detectors can be applied to extreme environments with high temperature and strong radiation. The total noise factor is most significantly influenced by the noise factor of the first stage in a cascade amplifier. Hence, the preamplifier must exhibit exceptional noise performance. The readout circuit is inevitably exposed to the influence of radiation, which may result in temporary or even permanent failure of electronic systems. The connection method between the SiC neutron detector and the readout circuit is typically DC-coupled. When the sensor is working, the leakage current generated by the sensor will enter the input end of the CSA and change the baseline position of the CSA. In this paper, a low-noise CSA with leakage current compensation circuit(LCC) is presented. The circuit’s voltage-to-charge amplification is 2.98mV/fC, and the error due to nonlinearity is below 0.01%. Without considering the input parasitic capacitance, ENC is 43.12e-. In addition, the circuit also has good radiation resistance and leakage current compensation function. It is implemented and simulated in the DB Hitek 0.18μm CMOS process model.

An improved low‐input resistance folded‐cascode transimpedance amplifier for giga‐bit per second optical communication front‐ends

SummaryThe present study is devoted to articulating a modified folded‐cascode circuit, to make folded‐cascode structures an attractive configuration as a transimpedance amplifier (TIA) for being employed in Giga‐bit per second optical communication receiver systems. Giga‐bps communication receivers are highly necessitating circuits to isolate the input parasitic capacitance of the photodiode. The present modification makes folded cascodes comparable to the famous regulated cascode (RGC) structures by isolating this parasitic capacitor almost by the same quantity. The system is shown to be capable of operating at 2.5 Gbps up to 8 Gbps data rate with a fixed bandwidth. The paper analyzes and evaluates the designed circuit mathematically, and the obtained simulated results from Cadence using TSMC 65 nm CMOS validate the suitability of the modified circuit as a TIA.

RESEARCH THE ACCURACY OF MODELING POWER LOSSES IN POWER DIODES AND TRANSISTORS

The methodology for modeling static and dynamic power losses in power IGBT and MOSFET transistors in the Matlab and Multisim software environments is given. It is shown that when modeling switching processes in power transistors, Matlab / Simulink does not allow determining the dynamic components of power losses, namely, the energy of turning on the transistor, the energy of turning off the transistor, as well as the recovery energy of power diodes. At the same time, the simulation of static power losses of power diodes and transistors in Matlab/Simulink is carried out with a significant error due to incorrect representation of the current-voltage characteristics. It is shown that for a more correct and accurate simulation of the operation of power transistors, including power losses in power switches, it is more appropriate to conduct simulations in the Multisim software environment, which takes into account more than 47 parameters during simulation, including temperature characteristics, parasitic input and output capacitances and inductances, nonlinearities of current-voltage characteristics and others. In Multisim, a circuit of a half-bridge inverter with power MOSFETs controlled by the IR2104PBF driver has been developed. It is shown that the switching of power transistors is significantly influenced by the parameters of the driver microcircuit, namely the size of the storage capacitor of the driver, as well as the value of the active resistance of the gate resistor. It is shown that the simulation in Multisim correctly displays the transient processes of turning on and off power transistors and reverse recovery of diodes, which allows determining the dynamic losses of power transistors and power diodes.

An Inductorless Optical Receiver Front-End Employing a High Gain-BW Product Differential Transimpedance Amplifier in 16-nm FinFET Process

In this paper, a fully-differential transimpedance amplifier (TIA) providing a high gain-BW product (GBP) is introduced. In the proposed architecture, a cascode cross-coupled structure is employed to double the effective transconductance of the cascode devices, improving the BW of the TIA. Moreover, a differential architecture is implemented using an RC high-pass filter along with a buffer stage requiring smaller capacitance and resistance. Furthermore, a single-ended negative capacitance generation (NCG) circuit is employed at the input of the TIA to partially compensate for the input parasitic capacitances. A TIA including the proposed techniques, designed and laid out in a 16-nm FinFET process, demonstrates 57% and 79% better figure-of-merit compared to cascode and conventional TIAs designed along with the proposed TIA for a fair comparison, respectively. Post-layout simulations in companion with statistical analysis are employed to verify the effectiveness of the proposed architecture. From simulation results, the optical receiver achieves a peak transimpedance gain of 58.5 dBΩ, a BW of 14.8 GHz, an input-referred noise of 33.6 pA/Hz, and an eye-opening of 30 mV at a data-rate of 56 Gbps PAM4 and at a bit-error-rate (BER) of 1E-6. The whole circuit consume 49 mW and occupies an active area of 0.0076 mm2.

CMOS-Driven VCSEL-Based Photonic Links: an Exploration of the Power-Sensitivity Trade-Off

This article explores the power-sensitivity trade-off in optical receivers aiming to improve the energy-efficiency of the overall link. Optical receivers with field-effect transistor (FET) front-ends (FEs) are usually designed for optimal noise performance by matching the circuit&#x2019;s input capacitance (<i>C_I</i>) to the total input parasitic capacitance (<i>C_D</i>). However, the receiver&#x2019;s power dissipation is also proportional to the input capacitance <i>C_I</i>. Therefore, this paper studies the feasibility of the capacitive matching rule in the context of minimizing the power dissipation of the overall link. For that purpose, design trade-offs for the receiver, transmitter, and the overall link are presented. Comparisons are made to study how much the receiver can be downsized, sacrificing optimal noise performance, before its power reduction is offset by the transmitter&#x2019;s increase in power. Simulation results show that energy-efficient links require low-power receivers with input capacitance much smaller than that required for noise-optimum performance. As an example, for a 25 Gb/s operation, an optical loss budget of 12.6 dB, and a receiver designed in 65 nm CMOS technology with <i>C_D</i> of 200 fF, the overall link dissipates 2.55 pJ/bit when the receiver&#x2019;s noise is minimized, leading to a receiver with <i>C_I</i>/<i>C_D</i> = 1.29. When optimized for overall link efficiency, the receiver size is significantly reduced to <i>C_I</i>/<i>C_D</i> = 0.38 and the link&#x2019;s energy-efficiency also improves to 1.41 pJ/bit. If the link budget or knowledge of the transmitter side is incomplete, our analysis indicates that maximizing gain with value of <i>C_I</i>/<i>C_D</i> = 0.5 is a reasonable choice.

Submicrowatt CMOS Rectifier for a Fully Passive Wake-Up Receiver

This work presents a wide-range, submicrowatt CMOS rectifier, which is designed to efficiently work at input power levels down to −31 dBm. The designed rectifier uses a novel threshold voltage compensation design, namely, the design of a custom-built single-stage rectifier that supplies a nanowatt current reference circuit. The generated bias current is mirrored to the core rectifier in order to precharge its CMOS diodes. The rectifier was optimized for a minimum number of gain stages while trying to minimize the overall input parasitic capacitance of the rectifier. The proposed CMOS rectifier was designed in an in-house 130-nm CMOS technology and includes a 1.6-kV human body level ESD protection at the input terminals. Measurements reveal a high 30% power conversion efficiency (PCE) over a wide input power range from −23 to −13 dBm for a 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{ M}}\Omega $ </tex-math></inline-formula> output load at 868 MHz. PCE of over 10% is achieved for a 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{ M}}\Omega $ </tex-math></inline-formula> load at an input power of −28 dBm. The enhanced startup at submicrowatt input power levels of the CMOS rectifier enables the design of an ultralow-power passive wake-up receiver. The measured sensitivity of −31 dBm for a 1-V output voltage across a capacitive load is the lowest reported in the literature so far.

A Tunable-Gain Transimpedance Amplifier for CMOS-MEMS Resonators Characterization.

CMOS-MEMS resonators have become a promising solution thanks to their miniaturization and on-chip integration capabilities. However, using a CMOS technology to fabricate microelectromechanical system (MEMS) devices limits the electromechanical performance otherwise achieved by specific technologies, requiring a challenging readout circuitry. This paper presents a transimpedance amplifier (TIA) fabricated using a commercial 0.35-µm CMOS technology specifically oriented to drive and sense monolithically integrated CMOS-MEMS resonators up to 50 MHz with a tunable transimpedance gain ranging from 112 dB to 121 dB. The output voltage noise is as low as 225 nV/Hz1/2—input-referred current noise of 192 fA/Hz1/2—at 10 MHz, and the power consumption is kept below 1-mW. In addition, the TIA amplifier exhibits an open-loop gain independent of the parasitic input capacitance—mostly associated with the MEMS layout—representing an advantage in MEMS testing compared to other alternatives such as Pierce oscillator schemes. The work presented includes the characterization of three types of MEMS resonators that have been fabricated and experimentally characterized both in open-loop and self-sustained configurations using the integrated TIA amplifier. The experimental characterization includes an accurate extraction of the electromechanical parameters for the three fabricated structures that enables an accurate MEMS-CMOS circuitry co-design.

Optimizing the Noise Performance of Multielectrode Image Charge Detectors Constructed on Printed Circuit Boards

In image charge sensing applications, a tradeoff exists between minimizing detector capacitance for improved amplifier noise performance and adding repeated sensing stages for noise improvement through averaging of repeated signals. In order to understand this tradeoff, the link between image charge detector geometry and capacitance is studied through finite element analysis. This knowledge is then used to present a novel method for determining the relevant detector parameters such that the system noise performance for a given amplifier is optimized. This method is independent of specific amplifier parameters. We find that the optimum noise performance does not lie in simply arbitrarily increasing the number of sensing stages, but depends on the amount of parasitic input capacitance to the amplifier. The greater the parasitic capacitance, the greater the number of stages for the optimum detector. The optimum number of stages is also highly dependent on the detector geometry.

The impact of active electrode guard layer in capacitive measurements of biosignals

This article presents an analysis of active electrode design for capacitively coupled measurement of bioelectrical signals. It deals with constructing an active electrode using a guard layer to decrease its input's parasitic capacitance. Three dielectric materials (cotton, polyester, wool) were examined under different pressure (1.23 kPa, 3.07 kPa) of the active electrodes. The Common Mode Rejection Ratio (CMRR) analysis of the system using guarded and unguarded electrodes is also investigated. The results show that the guard layer increases the active electrode's gain in the whole measured frequency range for all insulation materials and pressures. An unguarded active electrode reaches a gain of −7.45 dB while using cotton as dielectric material under the pressure of 1.23 kPa compared to the guarded active electrode, which reaches the gain value of −0.47 dB at the same conditions. The measurements of the CMRR prove that the guard layer increases the system CMRR.

Characterization of an architecture for front-end pixel binning in an integrating pixel array detector

Optimization of an area detector involves compromises between various parameters like frame rate, read noise, dynamic range and pixel size. We have implemented and tested a novel front-end binning design in a photon-integrating hybrid pixel array detector using the MM-PAD-2.0 pixel architecture. In this architecture, the pixels can be optionally binned in a 2×2 pixel configuration using a network of switches to selectively direct the output of 4 sensor pixels to a single amplifier input. Doing this allows a trade-off between frame rate and spatial resolution. Tests show that the binned pixels perform well, but with some degradation on performance as compared to an un-binned pixel. The increased parasitic input capacitance does reduce the signal collected per x-ray as well as increases the noise of the pixel. The increase in noise is, however, less than the factor of 2 increase one would observe for binning in post-processing. Spatial scans across the binned pixels show that no measured signal intensity is lost at the inner binning unit boundaries. In the high flux regime, at a 2×2 pixel wide beam spot (FWHM) size, binned mode responds linearly up to a photon flux of 107 x-rays/s, and performs comparably with un-binned mode up to a photon flux of 108 x-rays/s. While this study demonstrates a proof of concept for front-end binning in integrating detectors, we also identify changes to this early-stage prototype which can further improve the performance of binning pixel structures.

A Temperature-Stabilized Single-Channel 1-GS/s 60-dB SNDR SAR-Assisted Pipelined ADC With Dynamic Gm-R-Based Amplifier

A temperature-stabilized 12-bit single-channel successive approximation register (SAR)-assisted pipelined analog-to-digital converter (ADC) running at 1 GS/s with Nyquist signal to noise and distortion ratio (SNDR) above 60 dB is presented. The ADC uses a three-stage (4 b-4 b-6 b) SAR-assisted pipeline hybrid architecture to achieve an attractive energy efficiency along with an extended sampling rate. A high-linearity open-loop Gm-R-based residue amplifier (RA) with both complete-settled and dynamic features improves the residue amplification efficiency and speed, while reducing the gain variation over a temperature drift. The inter-stage gain variation over the temperature is compensated through complementary temperature coefficients (TCs) from the inner devices of the RA. Furthermore, a cascade amplification topology in the backend RA alleviates the effect of the input parasitic capacitance to its front-end capacitor DAC (CDAC), thus leading to a small CDAC size to accelerate amplification and conversion. The prototype ADC was fabricated in a 28-nm CMOS process and consumes 7.6 mW from a 1-V power supply at 1 GS/s. The measured inter-stage gain variation is less than 2.3% with a temperature range from 0 °C to 80 °C. The SNDR and SFDR are 60 and 74.6 dB with a Nyquist input, respectively, achieving a Walden figure-of-merit (FoM) of 9.3 fJ/conversion-step and a Schreier FoM of 168.2 dB.

High‐power broadband graphene non‐Foster circuit enabled class‐J GaN HEMT power amplifier

AbstractThis paper presents high‐power broadband graphene non‐Foster circuit (NFC) enabled Class‐J GaN HEMT power amplifier (PA). A graphene resonant‐tunneling diode (RTD) NFC is proposed to provide negative differential resistance characteristics and to create an effective negative capacitance. The NFC is integrated in the input matching network of the Class‐J GaN HEMT PA to cancel out the transistor input parasitic capacitance so as to enhance PA bandwidth, efficiency, output power, and gain. The PA design is based on Cree's packaged GaN HEMT CGHV40030F biased with drain supply voltage of 50 V at quiescent drain‐to‐source current of 44 mA. The PA operates from 3.4 to 4.0 GHz with center frequency of 3.7 GHz. The effective negative capacitance of the NFC from 3.4 to 4.0 GHz stands at −3.3 to −6.0 pF. An effective capacitance of −3.7 pF has been obtained at 3.7 GHz. The PA has small signal gain of 16.1 dB at 3.7 GHz. Large signal simulation input power sweep from 1 to 33 dBm at 3.7 GHz, indicates that the PA has 57.8% drain efficiency, 54.7% power added efficiency (PAE), 44.6 dBm (28.8 W) output power and 11.6 dB transducer power gain at input power of 33 dBm.

Interrogation Techniques and Interface Circuits for Coil-Coupled Passive Sensors.

Coil-coupled passive sensors can be interrogated without contact, exploiting the magnetic coupling between two coils forming a telemetric proximity link. A primary coil connected to the interface circuit forms the readout unit, while a passive sensor connected to a secondary coil forms the sensor unit. This work is focused on the interrogation of sensor units based on resonance, denoted as resonant sensor units, in which the readout signals are the resonant frequency and, possibly, the quality factor. Specifically, capacitive and electromechanical piezoelectric resonator sensor units are considered. Two interrogation techniques, namely a frequency-domain technique and a time-domain technique, have been analyzed, that are theoretically independent of the coupling between the coils which, in turn, ensure that the sensor readings are not affected by the interrogation distance. However, it is shown that the unavoidable parasitic capacitance in parallel to the readout coil introduces, for both techniques, an undesired dependence of the readings on the interrogation distance. This effect is especially marked for capacitance sensor units. A compensation circuit is innovatively proposed to counteract the effects of the parasitic input capacitance, and advantageously obtain distance-independent readings in real operating conditions. Experimental tests on a coil-coupled capacitance sensor with resonance at 5.45 MHz have shown a deviation within 1.5 kHz, i.e., 300 ppm, for interrogation distances of up to 18 mm. For the same distance range, with a coil-coupled quartz crystal resonator with a mechanical resonant frequency of 4.432 MHz, variations of less than 1.8 Hz, i.e., 0.5 ppm, have been obtained.

Design Considerations for a 100 Gbit/s SiGe-BiCMOS Power Multiplexer With 2 $V_{{\mathrm{pp}}}$ Differential Voltage Swing

This paper presents design considerations for an 8:1 multiplexer (MUX) circuit in a SiGe BiCMOS technology intended to be monolithically integrated together with a plasmonic Mach–Zehnder modulator on a single chip. It is shown why a power MUX (PMUX) architecture, where the final MUX selector stage directly drives the load, is beneficial to obtain high data rates and high output voltage swings at comparatively low power consumption. Therefore, the relation between the clock input amplitude and parasitic capacitances on the rise time of the PMUX is analyzed. Owing to the importance of the clock signal to the PMUX performance, design considerations for the clock distribution are presented. The design concept is proven by electrical measurements that demonstrate a record performance by clear output eye diagrams at 100 and 140 Gbit/s with 2.0 $V_{\text {pp}}$ and 1.2 $V_{\text {pp}}$ differential output voltage swing, respectively. The 2.6mm $\times $ 1.7mm MUX chip is implemented in IHP SG13G2 SiGe BiCMOS technology and consumes 7.15 W on a single −5.5-V supply voltage.

Capacitive analog front-end circuit with dual-mode automatic parasitic cancellation loop

This paper presents a capacitive analog front-end (AFE) integrated circuit (IC) with a dual-mode automatic parasitic cancellation loop. Capacitive AFEs are widely used for various capacitive microsensors based on micro-electro-mechanical system technologies. This paper presents a capacitive AFE IC with a dual-mode automatic parasitic cancellation loop. The capacitive AFE adopts the correlated double-sampling technique for low-noise characteristics. The automatic parasitic cancellation loop removes the unwanted offset caused by the input parasitic capacitances by implementing a successive approximation register scheme. The automatic parasitic cancellation loop includes two parts: a capacitor domain cancellation loop and a charge domain cancellation loop. The capacitor domain loop and charge domain loop execute coarse parasitic and fine parasitic cancellations, respectively. The chip is fabricated using the 0.18-μm complementary metal–oxide–semiconductor process and has an active area of 2.39 mm2. With the dual-mode parasitic cancellation loop, the input parasitic capacitance, ranging from −10.6 to 10.6 pF, can be cancelled with a resolution of 0.224 fF. The measured automatic offset cancellation time is lower than 14 ms. The power consumption is 928 μW with a 3.3 V supply.

A 12-Bit 10 MS/s SAR ADC With High Linearity and Energy-Efficient Switching

A 12-bit 10 MS/s SAR ADC with enhanced linearity and energy efficiency is presented in this paper. A novel switching scheme (COSS) is proposed to reduce the power consumption and the matching requirement for capacitors in SAR ADCs. The switching energy (including switching energy and reset energy), total capacitance and static performance (INL & DNL) of the proposed scheme are reduced by 98.08%, 75%, and 75%, respectively, compared with the conventional architecture. Based on analysis of the non-linear errors caused by comparator input parasitic capacitance, an improved comparator with push-pull pre-amplifier and output offset storage (OOS) strategy is proposed to diminish non-linearity in the input parasitic capacitance. The offset cancellation signal for the comparator can be generated by asynchronous timing automatically, without any extra clock. Additionally, an SFDR enhancement bootstrap switch is proposed to eliminate the distortion induced by parasitic capacitance and threshold voltage that results in insufficient precision for medium-speed 12-bit ADCs. The proposed ADC was fabricated in a 0.18 $\mu\text{m}$ 1P6M CMOS process, and the measured results show that the ADC achieves an SNDR of 66.9 dB and an SFDR of 75.8 dB with a 10 MS/s sampling rate and consumes 0.82 mW, resulting in a figure of merit (FOM) of 44.2 fJ/conversion-step. The peak DNL error is +0.36/−0.33 LSB, and the peak INL error is +0.55 LSB/−0.6 LSB. The ADC core occupies an active area of only $630 \mu\text{m}\! \times\! 570 \mu\text{m}^{2}$ .

Analysis of memory effect in amplifier-shared discrete-time sigma-delta modulators

In this paper, an analysis of the memory effect in two amplifier-shared switched-capacitor integrators for a discrete-time sigma-delta ($$\varSigma \varDelta$$ΣΔ) modulator is presented. Interaction between the integrators is modeled by feeding an integrator output voltage to another integrator input and vice versa and multiplying by a coefficient depending on DC gain and input parasitic capacitance of the opamp. The model is applied to a second-order $$\varSigma \varDelta$$ΣΔ modulator to analyze how signal and noise transfer functions are altered. The analysis reveals that the magnitude response of the signal transfer function is minimally affected in the low-frequency signal band, whereas that of the noise transfer function can be increased significantly in the signal band, degrading the effectiveness of noise shaping. In relation to the parasitic capacitance at the opamp input, the DC gain required of the opamp is derived quantitatively for a given degradation of modulator dynamic range with respect to different oversampling ratios. Considering leaky integration, which is also caused by the finite opamp DC gain, the DC gain requirement imposed by the memory effect is proved to be more severe than that by leaky integration. Macromodel-based circuit simulation results confirm the accuracy of the proposed model and equations.

Analysis and design of class E power amplifier considering MOSFET parasitic input and output capacitances

In this study, design theory and analysis for the class E power amplifier (PA), considering the metal oxide semiconductor field effect transistor (MOSFET) parasitic input and output capacitances, are proposed. The input resistance and capacitances cause non-ideal input voltage at gate terminal, which affect the specifications of the class E PA. In the proposed study, non-linear drain-to-source, linear gate-to-drain and linear gate-to-source MOSFET parasitic capacitances are considered, while zero voltage and zero derivative switching conditions are achieved. Moreover, the input resistance and the value of the input voltage are taken into account in the design theory. According to the obtained results, the duty cycle of the MOSFET depends on the MOSFET threshold voltage, input voltage, input series resistance, and some other parameters, which will be explained in this study. A design example is finally given to describe the design procedure at 1 MHz operating frequency along with the experimental result. The circuit simulation is also performed using PSpice software. The measured results showed quantitative agreements with simulation and theory results.

Non-Foster Matching of a Resistively Loaded Vee Dipole Antenna Using Operational Amplifiers

A non-Foster matching network using negative impedance converters (NICs) is proposed for a resistively loaded vee dipole antenna (RVD). The RVD suffers from considerable reflection at the feeding transmission line at low frequencies because of its large negative input reactance. To reduce the reflection, a non-Foster matching network, which is composed of NICs based on operational amplifiers (op-amps), is proposed. For the practical design, the effects of input parasitic capacitances of the op-amp and the finite open-loop gain are considered. The stability analysis is performed according to the Barkhausen stability criterion. The non-Foster matching network is implemented with the RVD as a load. The measured impedance demonstrates that the matching network significantly reduces the input reactance of the RVD. In the time-domain analysis, the matched RVD is shown to reflect significantly less incident pulse. A target was imaged through a series of radar echo experiments. The images show that the non-Foster matching network enhances the performance of the RVD as an antenna for the ground-penetrating radar.