Abstract

This work presents a wide-range, submicrowatt CMOS rectifier, which is designed to efficiently work at input power levels down to −31 dBm. The designed rectifier uses a novel threshold voltage compensation design, namely, the design of a custom-built single-stage rectifier that supplies a nanowatt current reference circuit. The generated bias current is mirrored to the core rectifier in order to precharge its CMOS diodes. The rectifier was optimized for a minimum number of gain stages while trying to minimize the overall input parasitic capacitance of the rectifier. The proposed CMOS rectifier was designed in an in-house 130-nm CMOS technology and includes a 1.6-kV human body level ESD protection at the input terminals. Measurements reveal a high 30% power conversion efficiency (PCE) over a wide input power range from −23 to −13 dBm for a 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{ M}}\Omega $ </tex-math></inline-formula> output load at 868 MHz. PCE of over 10% is achieved for a 1- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${\mathrm{ M}}\Omega $ </tex-math></inline-formula> load at an input power of −28 dBm. The enhanced startup at submicrowatt input power levels of the CMOS rectifier enables the design of an ultralow-power passive wake-up receiver. The measured sensitivity of −31 dBm for a 1-V output voltage across a capacitive load is the lowest reported in the literature so far.

Full Text
Published version (Free)

Talk to us

Join us for a 30 min session where you can share your feedback and ask us any queries you have

Schedule a call