InP Wafers Research Articles

Swift heavy ion induced structural evolution in InP

This article reports a comprehensive study on damage evolution in undoped InP due to 100 MeV silver (Ag7+) ion irradiation. Raman and Rutherford back scattering channeling (c-RBS) measurements are employed to bring out two different aspects of disorder in the system. While Raman spectroscopy revealed a monotonic increase in sub-surface strain due to ion irradiation, the later detected heavy damage in the wafer at high fluences. Furthermore, we have estimated the lattice temperature under above irradiation conditions in InP using a unified thermal spike model. The model includes both inelastic thermal spike and elastic collision spike along with the effect of latent heat. This model explains the observed damage evolution of the target. Above experimental techniques in conjunction with the simulation model provides a qualitative explanation of the damage accumulation leading to structural modification in the Ag ion-irradiated InP wafer.

(Invited) Combining SiGe BiCMOS and InP Processing in an on-top of Chip Integration Approach

The research on millimeter-wave circuits is driven by applications such as radar imaging and wideband communications. For some applications SiGe hetero junction bipolar transistors (HBTs) are limited in output power, determined by the physical properties of silicon. For SiGe devices with transit frequencies of 180 GHz a breakdown voltage BVCEO of 2.0 V can be measured. The increase in breakdown voltage means always a decrease in transit frequency. On the other hand, silicon is the leading material of modern semiconductor technology. It offers a high level of integration density and yield. SiGe-HBT device speed has increased to hundreds of gigahertz, however limited in output power compared to III-V semiconductor devices. Thus, merging the qualities of both III-V and Si technology will enable a new class of high-performance ICs.Our approach combines a 3” InP-DHBT transferred-substrate process [1] with a SiGe-BiCMOS process [2]. At first, silicon and InP wafers are processed separately. The silicon wafer runs through the complete production process with front-end and back-end in a 0.25 µm BiCMOS process with a five metal layers aluminum/tungsten back-end using silicon dioxide as interlayer dielectric and an additional tungsten local interconnect. The back-end-process was specially adapted for the following wafer bond process by planarization of the topmost metal (TM2) level. The InP wafer has a semi-completed front-end and one metal level of gold and benzocyclobutene (BCB) as the dielectric. At this stage the front-to-front bond process is performed (see Fig. 1 a). The ground metallization (Gd) of the InP wafer is embedded in BCB to achieve a surface step height of less than 100 nm. Prior to wafer bonding both wafers are spin coated with BCB. After a BCB curing process the two wafers are aligned and bonded. After the bond process the InP substrate is etched by HCl to expose the InP-DHBT structures (see Fig. 1 a). The vias between the InP and SiGe-BiCMOS structures are formed by inductively coupled plasma (ICP) reactive ion etching (RIE) dry etching through the BCB using SF6. Then they are electrically connected using a gold electroplating process (see Fig. 1 b).To demonstrate the capabilities of the heterointegration scheme an integrated signal source at 164 GHz was designed and fabricated [3]. It is an example of the different combinations of BiCMOS and InP circuit building blocks. It is shown in Fig. 2. The source consists of a fundamental voltage-controlled oscillator (VCO) in BiCMOS technology (left side in Fig. 2) which is interconnected by an optimized high frequency via transition to a doubler-amplifier combination in InP technology (right side of Fig. 2).Recently, the influences of the wafer bonding and the finalization of the InP-DHBT process on SiGe devices were investigated. It was found that the impact on the BiCMOS devices is rather small. The forward Gummel plot of a SiGe-HBT before and after hetero integration is shown in Fig. 3. There is a slight increase of the base current at low emitter-base voltages caused by leakage currents due to electrostatic discharges in etching processes in the post bonding procedure. But these changes are marginal. Nevertheless, options to remove these effects are being discussed, such as moderate anneal sequences (the post-fabrication temperature is limited to below 250°C due to the presence of BCB) and modifications to the post-waferbonding plasma etch recipes.

Invited: Heterointegration of Semiconductors: Challenges and Opportunities

Nowadays, semiconductor industry faces major challenges as the current materials and designs can hardly respond to the relentless course towards device miniaturization, higher performances, energy efficiency, cost-effectiveness, and multifunctionality, which have been the driving forces for the development of semiconductor technologies. New materials and integration processes are urgently needed to overcome these multi-faceted challenges. The heterointegration of dissimilar materials on the same platform has recently emerged as a powerful strategy to address some of these challenges. Particularly, tremendous efforts have been put to develop fabrication processes that allow the integration of III-V compound semiconductors on foreign substrates. For instance, III-V heterointegration on silicon substrates will enable the combination, within a single platform, III-V high-performance technologies with low cost and wafer size advantages besides its compatibility with standard semiconductor processing. In addition to electronic and optoelectronic applications, the realization of these hybrid substrates is also highly relevant for high-efficiency, low-cost photovoltaic cells, spintronics, bio-integrated technologies, to name a few. It is, however, noteworthy that this heterointegration needs to be achieved on the wafer level in order to be technologically and economically viable. In this presentation, we provide a description of important approaches to achieve this heterogeneous integration, with an emphasis on wafer bonding processes and thin layer splitting using the ion-cut process. A variety of bulk-quality heterostructures, frequently unattainable by direct epitaxial growth, can be produced provided that a list of technical criteria is fulfilled, thus offering an additional degree of freedom in the design and fabrication of heterogeneous, multifunctional, and flexible devices. Ion cutting is a generic process that can be employed to split and transfer fine monocrystalline layers from various crystals. Materials and engineering issues as well as our current understanding of the underlying physics involved in its application to cleaving thin layers from freestanding GaN, InP, and GaAs wafers will be presented and discussed.

Growth of High-Quality Arbitrary-Shape Compound Semiconductors on Non-Epitaxial Substrates for Photovoltaic and Optoelectronic Device Applications

A method for direct growth of optoelectronic quality III-V semiconductors on non-epitaxial substrates will be discussed. Specifically, structures with geometries ranging from micro/nanostructures to ultra-large grain polycrystalline thin films may be grown via a phase transformation technique where the group III element is first deposited in the desired geometry and subsequently exposed to a vapor of the group V element. By careful control over nucleation and growth of the resulting III-V semiconductor, arbitrarily shaped III-V structures may be grown on non-epitaxial substrates. First, the general method for this growth will be discussed, showing how different structures and geometries may be obtained using InP as a model system. Next characterization of the InP films obtained will be presented, showing that films grown via this method on metal foils exhibit mobilities of ~500 cm^2/V-s, minority carrier lifetimes of >2 ns, and radiative efficiencies comparable to single crystal InP wafers. Additionally, methods for control over nucleation are demonstrated, showing that single crystalline structures >100 um in diameter may be easily obtained and, with proper tuning, mm scale crystals may be grown on non-epitaxial substrates. Furthermore, the use of this nucleation and growth control will be used to demonstrate InP for electronic and optoelectronic applications.

Effects of thermal treatment on radiative properties of HVPE grown InP layers

Radiative efficiency of highly luminescent bulk InP wafers severely degrades upon heat treatment involved in epitaxial growth of quaternary layers and fabrication of photodiodes on the surface. This unfortunate property impedes the use of bulk InP as scintillator material. On the other hand, it is known that thin epitaxial InP layers, grown by molecular beam epitaxy (MBE) or metal–organic chemical vapor deposition (MOCVD), do not exhibit any degradation. These layers, however, are too thin to be useful in scintillators. The capability of hydride vapor phase epitaxy (HVPE) process to grow thick bulk-like layers in reasonable time is well known, but the radiative properties of HVPE InP layers are not known. We have studied radiative properties of 21μm thick InP layers grown by HVPE and found them comparable to those of best luminescent bulk InP virgin wafers. In contrast to the bulk wafers, the radiative efficiency of HVPE layers does not degrade upon heat treatment. This opens up the possibility of implementing free-standing epitaxial InP scintillator structures endowed with surface photodiodes for registration of the scintillation.

Design and Fabrication of Wide Wavelength Range 25.8-Gb/S, 1.3-μM, Push-Pull-Driven DMLs

We design and fabricate wide wavelength range directly modulated lasers (DMLs) on the same InP wafer to realize a large-capacity monolithically integrated light source array up to 1 Tb/s. We demonstrate a 25.8-Gb/s push-pull operation over a 30-nm wavelength range, which is conventionally about 14 nm for 100 GbE applications. To extend the operating wavelength range, we design the wavelength dependence of the differential gain (∂G/∂n) for an InGaAlAs multiple quantum well structure, and realize high frequency relaxation oscillation resulting from the high differential gain over a wide range. Next, we also design the wavelength detuning (Δλ) under an operating injection current condition by taking account of the thermal effect of the chip, because Δλ determines ∂G/∂n, and the threshold current of the laser diode (LD). In addition, to achieve a 25.8-Gb/s push-pull operation, we fabricate a ridge waveguide structure buried in benzocyclobutene (BCB) with a low parasitic capacitance, and electrically isolate the DML from the neighboring chip by etching off n-InP. By using this design and structure, we achieve a 3-dB-down frequency bandwidth of over 20 GHz from 1290 to 1320 nm. We also achieve a mean output power of 8.0 dBm, and a dynamic extinction ratio of 5 dB. We measure the 25.8-Gb/s transmission characteristics, and obtain clear eye openings for a back-to-back configuration. We also measure the bit-error-rate performance, and obtain error-free operation for a 30-nm operating wavelength range.

Electrodeposition of High-Purity Indium Thin Films and Its Application to Indium Phosphide Solar Cells

We report on advances in the electrochemical deposition of indium (In) on molybdenum foil that enables deposition of electronic-grade purity, continuous films with thickness in the micron range. The desired In film morphology is obtained from an InCl3 aqueous bath by using a high current density of 250 mA/cm2 and a low deposition-bath temperature of −5°C to increase the nucleation density of In islands until a continuous film is obtained. As an example application, the electrodeposited In films are phosphorized via the thin-film vapor-liquid-solid growth method. The resulting poly-crystalline InP films display excellent optoelectronic quality, comparable to single crystalline InP wafers, thus demonstrating the versatility of the developed electrochemical deposition procedure.

Edge excitation geometry for studying intrinsic emission spectra of bulk n-InP

The shape of the photoluminescence line excited at an edge face of InP wafer and registered from the broadside is used to investigate the intrinsic emission spectrum. The procedure is much less sensitive to the surface properties and the carrier kinetics than the conventional methods used with the reflection or transmission geometry of photoluminescence. Our method provides a tool for studying the effects of non-equilibrium distribution of minority carriers in doped direct-band semiconductors.

Quantitative Analysis of the Metallic Contamination On GaAs and InP Wafers By TXRF and ICPMS Techniques

not Available.

Dislocations related with the pore on P‐rich InP wafer

AbstractThe two dimension distributions of dislocation and thermal stress of 3‐inch diameter stoichiometric and P‐rich InP wafers are investigated, and an analysis of the relation between the two distributions is given. As a result, in stoichiometric and P‐rich InP wafers, both the dislocation and thermal stress distributions are found to be circular ring shape, and where the thermal stress is stronger, the etch‐pits density (EPD) is higher, too. On the P‐rich wafers, there are some pores where EPD is much higher than other areas, around most pores, thermal stress is very strong, but around a small number of pores, the thermal stress is weaker as a contrary, that may be because the residual thermal stress can be released along the pores penetrating through the ingot during ingot annealing. Thermal stress is one of the main reasons which can contribute to dislocation. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Quantitative Analysis of the Metallic Contamination On GaAs and InP Wafers by TXRF and ICPMS Techniques

The quantitative analysis of the metallic contaminants both by chemical collection coupled to ICPMS and TXRF were implemented on GaAs and InP 100mm wafers. VPD-DC-ICPMS and LPD-ICPMS were developed respectively for GaAs and InP substrates. These methods present CE higher than 85% for usual metallic contaminants except for Cu & noble metals, and very sensitive detection thresholds are reached (108 to 1011 at/cm²). TXRF analysis conditions were optimized on both substrates. Na, Mg, Al, Ir and Ge on GaAs and K, Ca, Pd and Ag on InP are not analyzable due to substrate interferences. TXRF calibration was carried out from intentionally contaminated wafers in reference to ICPMS methods. Finally, TXRF enables to reach interesting detection limits (1010 to 1012 at/cm² range) and is able to measure Cu and some noble metals.

Radially polarized terahertz waves from a photoconductive antenna with microstructures

The generation of radially polarized terahertz (THz) waves from a photoconductive antenna (PCA) with radial microstructures was investigated. Microstructured electrodes with 10 μm lines and spaces were fabricated on a semi-insulating InP wafer using photolithography. The PCA with three layers was driven by an amplified femtosecond laser and DC power supply. Radially polarized THz waves from the PCA were measured by a Michelson interferometer with a 4.2 K silicon bolometer. The polarization components of THz waves were analyzed by a wire grid polarizer.

Improvement of the surface quality of semi-insulating InP substrates through a novel etching and cleaning method

Residual impurities and contamination on semi-insulating (SI) InP wafers are detrimental for epitaxial growth and device performance, especially because residual silicon on an SI-InP wafer surface is electrically active and generates an n-type conduction layer at the interface between the epilayer and the InP substrate. In order to reduce the concentration of Si and improve surface quality, the authors investigate a wet-chemical cleaning process for ready-to-use InP substrates. A novel and practical cleaning process was developed by adding an alkaline solution to the conventional acidic cleaning process. Time-of-flight secondary mass spectrometry, a very powerful analysis technique to characterize surfaces and investigate any organic and inorganic contamination present on the InP surface, was used after the samples were etched under different cleaning processes. The results show that the novel etching process effectively reduces the Si contamination.

Hydrogen Sensors Made on InP or GaN with Electrophoretically Deposited Pd or Pt Nanoparticles

High quality Schottky diodes were prepared by printing colloidal graphite on the polished wafers of n-type InP or n-type GaN. The wafers were earlier sparsely covered with palladium or platinum nanoparticles by electrophoresis from prepared colloid solutions in isooctane. Deposited contacts and nanoparticles were observed by scanning electron mictroscopy. Current voltage characteristics of the Schottky diodes showed high recti cation ratios and the barrier heights close to the value of vacuum-level-alignment of the Schottky Mott limit. The sensitivity to hydrogen of the diodes was measured in the ow of hydrogen/nitrogen mixtures of various hydrogen concentrations in the range from 1 ppm to 1000 ppm. The estimated detection limits of the diodes were in the sub-ppm range. The diodes represent orders-of-magnitude improvement over the best hydrogen sensors reported previously.

Electron-mediated ferromagnetism in Fe-doped InP: Theory and experiment

We report on the electron-mediated ferromagnetism in Fe-doped InP from both first-principles calculations and experiments. Theoretically, based on the spin-polarized density functional theory within the Heyd—Scuseria—Ernzerhof (HSE03) approach, we systematically investigate the magnetic properties of Fe-doped InP and predict the existence of electron-mediated ferromagnetism. Experimentally, by diffusing Fe into the n-type InP wafer with thermal annealing at 800 °C, we observe room-temperature ferromagnetism in InP:Fe, which is in agreement with the theoretical prediction.

Reflectance reduction of InP wafers after high-temperature annealing

Broadband reduction of light reflection from the surface of InP wafers after high-temperature annealing in air has been observed. In the transparency region of the material, the reflection drop is accompanied by increasing transmission of light through the wafer. The spectral position of a deep minimum of the reflection coefficient can be tuned, by varying the temperature and the time of annealing, in a wide spectral range from ultraviolet to infrared. The effect is due to formation of thermal oxide layers on the surfaces of the wafer with optical parameters favorable for antireflection.

Influence of annealing temperature on magnetic properties of InFeP prepared by ion implantation

InFeP layers were prepared by implantation of 5×1016 Fe+/cm2 into InP wafers followed by thermal annealing at 300–600°C. The samples were studied by atomic force microscopy, magnetic force microscopy, and superconducting quantum interference device, which showed the existence of magnetic clusters on surface of samples annealed at high temperatures and clear ferromagnetic behavior with a Curie temperature exceeding room temperature. High temperature annealing tends to degrade the magnetic properties. The ferromagnetism of the Fe-implanted InP samples is interpreted by double exchange of d-electrons in the impurity band and ferromagnetic clusters (InFe alloy, Fe or Fe3P).

Low Temperature Direct Bonding of InP and Si3N4-Coated Silicon Wafers for Photonic Device Integration

Low temperature (200°C) direct bonding of InP and Si3N4 coated silicon wafers using oxygen plasma surface treatment has been demonstrated, which transfers InP-based thin films onto Si substrates for heterogeneous photonic integration. Pulling test shows a high bonding energy comparable to the InP fracture energy. The high crystalline quality of the bonded thin film is preserved, as evident from photoluminescence and high resolution X-ray diffraction measurements. Cross-sectional transmission electron microscopy shows an intimately bonded interface with no observable defects generated near the bonded interface. A thin layer of amorphous oxide about 6 nm thick has been detected at the bonded interface. The hydrophilic interface obtained by oxygen plasma activation helps to achieve high quality bonding. Due to the high thermal conductivity of Si3N4, these high quality bonded structures of InP/Si with Si3N4 sandwiched in-between have potential applications in enhancing performance of high power Si photonic integrated devices.

Highly sensitive hydrogen sensor based on graphite-InP or graphite-GaN Schottky barrier with electrophoretically deposited Pd nanoparticles

Depositions on surfaces of semiconductor wafers of InP and GaN were performed from isooctane colloid solutions of palladium (Pd) nanoparticles (NPs) in AOT reverse micelles. Pd NPs in evaporated colloid and in layers deposited electrophoretically were monitored by SEM. Diodes were prepared by making Schottky contacts with colloidal graphite on semiconductor surfaces previously deposited with Pd NPs and ohmic contacts on blank surfaces. Forward and reverse current-voltage characteristics of the diodes showed high rectification ratio and high Schottky barrier heights, giving evidence of very small Fermi level pinning. A large increase of current was observed after exposing diodes to flow of gas blend hydrogen in nitrogen. Current change ratio about 700,000 with 0.1% hydrogen blend was achieved, which is more than two orders-of-magnitude improvement over the best result reported previously. Hydrogen detection limit of the diodes was estimated at 1 ppm H2/N2. The diodes, besides this extremely high sensitivity, have been temporally stable and of inexpensive production. Relatively more expensive GaN diodes have potential for functionality at high temperatures.

Active Integrated Filters for RF-Photonic Channelizers

A theoretical study of RF-photonic channelizers using four architectures formed by active integrated filters with tunable gains is presented. The integrated filters are enabled by two- and four-port nano-photonic couplers (NPCs). Lossless and three individual manufacturing cases with high transmission, high reflection, and symmetric couplers are assumed in the work. NPCs behavior is dependent upon the phenomenon of frustrated total internal reflection. Experimentally, photonic channelizers are fabricated in one single semiconductor chip on multi-quantum well epitaxial InP wafers using conventional microelectronics processing techniques. A state space modeling approach is used to derive the transfer functions and analyze the stability of these filters. The ability of adapting using the gains is demonstrated. Our simulation results indicate that the characteristic bandpass and notch filter responses of each structure are the basis of channelizer architectures, and optical gain may be used to adjust filter parameters to obtain a desired frequency magnitude response, especially in the range of 1–5 GHz for the chip with a coupler separation of ∼9 mm. Preliminarily, the measurement of spectral response shows enhancement of quality factor by using higher optical gains. The present compact active filters on an InP-based integrated photonic circuit hold the potential for a variety of channelizer applications. Compared to a pure RF channelizer, photonic channelizers may perform both channelization and down-conversion in an optical domain.