InGaZnO TFTs Research Articles

P‐21: Post‐Annealing Optimization for Top‐Gate Amorphous In‐Ga‐Zn‐O Thin‐Film Transistors with Atomic‐Layer‐Deposited Ultrathin AlOx Dielectric

The effects of post‐annealing on amorphous InGaZnO (a‐IGZO) TFTs with ultrathin atomic layer deposited (ALD) AlOxgate insulator (GI) were investigated. The non‐annealed devices exhibited uncontrollable gate leakage current while postannealing in either oxygen (O2) or nitrogen (N2) exhibited noticeable improvements. Optimizing O2‐annealed devices demonstrated the most optimal performance, including a low subthreshold swing of 61.6 mV/dec and a high on/off current ratio over 109. Capacitance‐voltage and X‐ray photoelectron spectroscopy analyses further revealed the underlying mechanism of defect elimination at the AlOx/a‐IGZO interface.

Embedded Gate Driver Circuit With Self-Aligned InGaZnO TFTs Using Common Bootstrapped Capacitive Driving for High-Resolution WOLED Displays

Embedded Gate Driver Circuit With Self-Aligned InGaZnO TFTs Using Common Bootstrapped Capacitive Driving for High-Resolution WOLED Displays

Direct Observation for Distinct Behaviors of Gamma‐Ray Irradiation‐Induced Subgap Density‐of‐States in Amorphous InGaZnO TFTs by Multiple‐Wavelength Light Source

Direct Observation for Distinct Behaviors of Gamma‐Ray Irradiation‐Induced Subgap Density‐of‐States in Amorphous InGaZnO TFTs by Multiple‐Wavelength Light Source

Channel Nanoscaling of InGaZnO TFTs and Circuits via Focused Ion Beam

Channel Nanoscaling of InGaZnO TFTs and Circuits via Focused Ion Beam

High-Performance of InGaZnO TFTs With an Ultrathin 5-nm Al₂O₃ Gate Dielectric Enabled by a Novel Atomic Layer Deposition Method

High-Performance of InGaZnO TFTs With an Ultrathin 5-nm Al₂O₃ Gate Dielectric Enabled by a Novel Atomic Layer Deposition Method

AC Performance Tunability of Flexible Bottom-Gate InGaZnO TFTs by an Additional Top-Gate Contact

AC Performance Tunability of Flexible Bottom-Gate InGaZnO TFTs by an Additional Top-Gate Contact

24‐2: Facile Design of Integrated Gate Driver Circuit with Self‐aligned InGaZnO TFTs and Reliable Compensation Technology for 166 PPI WOLED Displays

In this research, we describe a facile design of white organic light emitting diode (WOLED) displays applicable to 8K4K resolution of large‐area displays. We demonstrated a 13.3‐inch diagonal size (166 pixel‐per‐inch) of WOLED display, including a self‐aligned oxide thin‐film transistors, simple pixel driving circuit, external compensation method, fast driving integrated gate driver circuit. The narrow bezel of 3.9 mm is realized when multi‐output gate driver circuit is applied. The required function for external compensation method is realized by the integrated gate driver circuit. The external compensation improved global luminance uniformity, especially at the low gray level.

Influence of Semiconductor Island Geometry on the AC Performance of Flexible InGaZnO TFTs

The AC performance of flexible TFTs sufferers from parasitics caused by tolerances needed for the fabrication on free-standing plastic foils. In this context, the semiconductor island can either be wider or narrower than the source/drain contacts. Traditionally, the second configuration is expected to result in faster TFTs as the total gate overlap area is smaller. However, here it is shown that 2.5 μm long flexible InGaZnO TFTs with wide semiconductor islands exhibit better frequency performance such as a f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 26.1MHz (compared to f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> of 13.8MHz of TFTs with narrow semiconductor islands). This effect is confirmed for flat and bend TFTs and is caused by current spreading in the semiconductor islands, as well as the frequency dependency of the gate capacitance.

High-Performance Self-Aligned Top-Gate Amorphous InGaZnO TFTs With 4 nm-Thick Atomic-Layer-Deposited AlOx Insulator

Electrical characteristics of self-aligned top-gate (SATG) amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) with 4 nm-thick atomic-layer-deposited (ALD) AlO_x gate insulator (GI) are investigated. It is demonstrated that the SATG a-IGZO TFTs present high-performance metrics including a near-ideal subthreshold swing (<i>SS</i>) of 60.9 mV/dec, a low off-state current below 10^&#x2212;12 A, a positive <inline-formula> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> of 0.1 V, and a decent mobility of 14.1 cm²/<inline-formula> <tex-math notation="LaTeX">$\text{V}\,\cdot $ </tex-math></inline-formula>s. In addition, the TFTs exhibit negligible <inline-formula> <tex-math notation="LaTeX">${V}_{\text{th}}$ </tex-math></inline-formula> shifts less than 0.02 V against electrical bias stresses. Both high performance and excellent stability are thus simultaneously achieved for the ultrathin GI of amorphous oxide semiconductor (AOS) TFTs.

Mobility Enhancement and Abnormal Humps in Top-Gate Self-Aligned Double-Layer Amorphous InGaZnO TFTs

The mobility enhancement and the positive bias stress of top-gate self-aligned TFTs using the a-IGZO channel with a front barrier are investigated. The a-IGZO front barrier can keep electrons in the a-IGZO channel away from the top-gate oxide to significantly enhance the electron mobility at the top gate operation. The parasitic channel induces a hump in the transfer characteristics. The positive bias stress shifts the hump to the negative voltage abnormally. The H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O in the polymer film on array layer is responsible for the abnormal shift. The H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O diffuses into the top-gate insulator and is electrolyzed to create H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> , which forms a parasitic channel with a negative shift of threshold voltage, leading to the abnormal hump. The abnormal humps are increasingly significant with the increasing channel width and the decreasing channel length. The channel width dependence on positive bias stress is due to the inverse narrow width effect caused by the fringe electric field. The channel length dependence on positive bias stress is due to the H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> diffusion toward the center of the parasitic channel from both the source and drain sides.

Short-Channel Top-Gate InGaZnO Thin-Film Transistors Fabricated With Boron Implantation Into Source/Drain Regions

In this brief, we discuss top-gate InGaZnO thin-film transistors (InGaZnO TFTs) fabricated with boron (B) implantation into the source–drain regions, focusing on channel shortening. B was implanted through the gate insulator into the InGaZnO layer. From scanning capacitance microscopy (SCM) analysis, we found that boron implantation in the S/D regions of InGaZnO TFTs induces channel shortening. We also found that such channel shortening is suppressed by optimizing acceleration voltage in the boron implantation process, leading to good operation in short-channel ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$1.5~\mu \text{m}$ </tex-math></inline-formula> ) InGaZnO TFT.

P‐15: Student Poster: Reliable Gate Driver for Real‐Time External Compensated AMOLED Display Using InGaZnO TFTs

The a‐IGZO TFTs integrated gate driver circuit with inter‐frame memory module and isolated bootstrapping node structure is proposed for AMOLED display. The driver can provide progressive display signal, inter‐frame detection signal and standby detection signal. Compared with conventional ones, the proposed inter‐frame memory shows enhanced driving ability due to the introduce of voltage bootstrapping function. Besides, the proposed gate driver can tolerate larger threshold voltage variations (ΔVth) than the conventional circuit due to the isolated bootstrap node structure.

(Invited) Device Scalability of InGaZnO TFTs for Next-Generation Displays

Device scaling of thin-film transistors has only recently gained attention, as the need has grown for shorter channel lengths in hybrid integration applications as well as a performance enhancer in future displays. In this study, we study the device scalability of short-channel top-gate oxide TFTs down to 1 mm, with particular focus on the carrier profile at the channel edges. We propose a carrier profile extraction method by utilizing comprehensive simulation fitting of the effective channel length, threshold voltage roll-off to the measured and extracted values. We find that the effective channel length plays an important role at short-channel lengths, and the scalability can be improved by adjusting the process-dependent carrier concentration profile.

Improving Electrical Stability of a-InGaZnO Thin-Film Transistors with Thermally Deposited Self-Assembled Monolayers

Amorphous InGaZnO (a-IGZO) TFTs become mainstream at the forefront of display backplanes and are actively expanding their area for next-generation optoelectronic devices such as flexible and transparent displays. For flexible displays, low temperature processed passivation technology is required to keep the reliability of the electrical properties in a-IGZO TFTs without damaging flexible plastic substrates. Here, we proposed a low-temperature passivation process using a dual-chamber system. A high-quality passivation layer composed of octadecyl-trichlorosilane was formed at 140 °C under vacuum on the back-channel of a-IGZO TFTs using the system. The thermally deposited self-assembled monolayers (SAMs) enable the formation of hydrophobic surfaces on a-IGZO TFTs, leading to the protection of the back-channel against water and oxygen efficiently. As a result, the electrical characteristics such as the threshold voltage shift, hysteresis, field-effect mobility, and negative bias stress of the SAM treated TFTs were significantly improved compared to those of the control TFTs.

Abnormal Hump Effect Induced by Hydrogen Diffusion During Self-Heating Stress in Top-Gate Amorphous InGaZnO TFTs

The mechanism of hydrogen-diffusion-induced electrical degradation under the self-heating effect for a top-gate amorphous InGaZnO (a-IGZO) thin-film transistor is examined in this article. Joule heating occurs in channels under high operating currents. The hydrogen in the <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{n}^{+}$ </tex-math></inline-formula> a-IGZO source/drain then diffuses into the channel and shifts the threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{{\text {TH}}}$ </tex-math></inline-formula> ) in the negative direction. As the thermal conductivity of a-IGZO is lower than that of the surrounding insulator, the heat is preferentially dissipated from the sides of the channel. However, the heat in the center of the channel cannot by dissipated quickly. In addition, the unequal channel thermal effect induces a hump effect in the electrical characteristics, which is observed in COMSOL simulations. Hydrogen diffusion under self-heating stress (SHS) operation increases both the effective channel length and parasitic capacitance. The capacitance measurement method is used to clarify the mechanisms of these abnormal phenomena. Finally, the Joule heating effect is eliminated in a low-temperature environment at 200 K with a constant current, confirming that the degradation is indeed caused by the Joule heating effect.

Study on Top-Gate Self-Aligned InGaZnO TFTs on PI Substrate

Study on Top-Gate Self-Aligned InGaZnO TFTs on PI Substrate

Study on Top-Gate Self-Aligned InGaZnO TFTs on PI Substrate

Study on Top-Gate Self-Aligned InGaZnO TFTs on PI Substrate

P‐1.16: Top‐gate Self‐aligned InGaZnO TFTs with Copper Light Shield Layer

In this paper, top‐gate self‐aligned a‐IGZO TFTs with copper light shield layer were fabricated. In order to prevent Cu oxidation phenomenon, a SiNx buffer interlayer layer was added. TFT with SiNx buffer interlayer shows excellent VTH uniformity on Gen. 4.5 glass and good PBTS and NBTIS reliability. After these optimization of the thickness of SiNx layer, the Vth shift of PBTS and NBTIS could be improved to 0.5 V and ‐0.8 V.

38.4: Top‐Gate Self‐Aligned InGaZnO TFTs with High PBTS Reliability by Employing Different H‐Incorporation Process

In this paper, we have demostrated high PBTS top‐gate self‐aligned IGZO TFTs by employing different H‐incorration process. Through optimization processes, PBTS is improved to 0.29 V and Vth deviation on Gen. 4.5 glass is 0.4V. Finally, 31‐inch OLED TV employing GOA circuit applied by this optimized backplane was successfully demonstrated.

30‐2: Top‐Gate Self‐Aligned InGaZnO TFTs with High PBTS Reliability by Employing Different H‐Incorporation Process

In this paper, we have demostrated high PBTS top‐gate self‐aligned IGZO TFTs by employing different H‐incorration process. Through optimization processes, PBTS is improved to 0.29 V and Vth deviation on Gen. 4.5 glass is 0.4V. Finally, 31‐inch OLED TV employing GOA circuit applied by this optimized backplane was successfully demonstrated.