InGaAs Metal-oxide-semiconductor Field-effect Transistors Research Articles

Attainment of low subthreshold slope in planar inversion-channel InGaAs MOSFET with in situ deposited Al2O3/Y2O3 as a gate dielectric

We have demonstrated a record low 85 mV dec−1 subthreshold slope (SS) at 300 K among the planar inversion-channel InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs). Our MOSFETs using in situ deposited Al2O3/Y2O3 as a gate dielectric were fabricated with a self-aligned inversion-channel gate-first process. The temperature-dependent transfer characteristics showed a linear reduction of SS versus temperature, with the attainment of an SS of 22 mV dec−1 at 77 K; the value is comparable to that of the state-of-the-art InGaAs FinFET. The slope factor of SS with temperature (m) is 1.33, which is lower than those reported in the planar InGaAs MOSFETs.

Effects of Equivalent-Oxide-Thickness and Fin-Width Scaling on In0.53Ga0.47As Tri-Gate Metal-Oxide-Semiconductor-Field-Effect-Transistors with Al2O3/HfO2 for Low-Power Logic Applications

We created tri-gate sub-100 nm In0.53Ga0.47As metal-oxide-semiconductor-field-effect-transistors (MOSFETs) with a bi-layer Al2O3/HfO2 gate stack and investigated the scaling effects on equivalent-oxide-thickness (EOT) and fin-width (Wfin) at gate lengths of sub-100 nm. For Lg = 60 nm In0.53Ga0.47As tri-gate MOSFETs, EOT and Wfin scaling were effective for improving electrostatic immunities such as subthreshold swing and drain-induced-barrier-lowering. Reliability characterization for In0.53Ga0.47As Tri-Gate MOSFETs using constant-voltage-stress (CVS) at 300K demonstrates slightly worse VT degradation compared to planar InGaAs MOSFET with the same gate stack and EOT. This is due to the effects of both of the etched fin’s sidewall interfaces.

Modulation of sub-threshold properties of InGaAs MOSFETs by La2O3 gate dielectrics

We have found the ferroelectric-like characteristics in atomic layer deposition (ALD) La2O3 films with thermal budget lower than 300oC in polarization-electric field (P-E) and capacitance-gate voltage (C-V) measurements on W/La2O3/W and W/La2O3/InGaAs capacitors. The observed hysteresis and saturation of polarization in the P-E characteristics of the W/La2O3/W and the W/La2O3/InGaAs capacitors, and the counter-clockwise C-V hysteresis in the C-V curves of the W/La2O3/InGaAs capacitors suggest a possibility of ferroelectricity in the present La2O3 films. By using this gate stack, W/La2O3/InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) were fabricated in order to examine the negative capacitance (NC) effect due to La2O3. It is found that the sub-threshold swing (SS) of W/La2O3/InGaAs MOSFETs is lower at low temperature than the theoretical limit of MOSFETs. This result strongly suggests that the W/La2O3/InGaAs MOSFETs can work as a steep-slope III-V negative capacitance field-effect transistor (NCFET).

Long‐channel In 0.7 Ga 0.3 As/In 0.52 Al 0.48 As quantum‐well MOSFETs on InP substrate with record μ n_eff = 6960 cm 2 /V‐s

Long-channel In0.7Ga0.3As/In0.52Al0.48As quantum-well (QW) metal-oxide-semiconductor field-effect-transistors (MOSFETs) on InP substrate have been fabricated and characterised. The fabricated device with Lg = 4 μm exhibits excellent maximum transconductance (gm_max ) in excess of 0.48 mS/μm at V DS = 0.95 V, together with reasonably good electrostatic integrity of drain-induced-barrier-lowering < 40 mV/V and subthreshold-swing <100 mV/decade. Besides, the effective mobility (μn_eff ) of the same device has been extracted, revealing that the device in this work yields excellent μn_eff = 6960 cm2/V-s at room temperature. To the knowledge of the authors, the value of μn_eff in this work is the highest in any surface-channel InGaAs MOSFET technology.

Record Effective Mobility Obtained From In0.53Ga0.47As/In0.52Al0.48As Quantum-Well MOSFETs on 300-mm Si Substrate

In this letter, we have investigated the properties of In0.53Ga0.47As quantum-well (QW) metal–oxide–semiconductor field-effect-transistors (MOSFETs) on a 300-mm(100) Si wafer. We have explored the impact of scaling down In0.53Ga0.47As channel thickness ( $\text{t}_{\mathrm {ch}})$ from 15 to 5 nm. The fabricated devices show excellent electrostatic integrity, such as subthreshold-swing (SS) $\mu _{\textit {n$\_{}$eff}})$ of the fabricated devices to investigate the carrier transport properties of the InGaAs MOSFETs with different values of $\text{t}_{\mathrm {ch}}$ . The device with $\text{t}_{\mathrm {ch}} = 15$ nm displayed a value of $\mu _{\textit {n$\_{}$eff}} = 2,190$ cm2/V-s at room temperature. This valuewas found to decrease as $\text{t}_{\mathrm {ch}}$ was scaled down.

(Invited) An Investigation of the InGaAs MOS System for Future High Mobility Channel Applications

As silicon devices reach the limit of dimensional scaling there is a growing interest in the use of high electron mobility channels, such as InxGa1-xAs, in conjunction high dielectric constant (high-k) gate oxides for n-channel Metal-Oxide-Semiconductor Field Effect Transistors (MOSFETs) in FinFET structures [1] and in 3D integration schemes [2]. The understanding and control of electrically active defect states at the high-k/InxGa1-xAs interface and of charges within the atomic layer deposited (ALD) high-k films will be essential for the successful implementation of high mobility channel materials in MOSFET or tunnel FET configurations. The objective of this presentation will be to provide an overview of the current understanding of the density and distribution of electrically active defects at the high-k/InGaAs interface and of defect states located in the interfacial oxide transition region which are manifest as accumulation frequency dispersion and capacitance-voltage hysteresis. The presentation will focus on InGaAs with a 53% Indium concentration. The electrically active interface state density distribution is determined from fully fabricated InGaAs MOSFET structures based on the full gate capacitance in conjunction with the Maserjian Y-function and Poisson-Schrodinger simulations [3]. Comparisons to simulations will be discussed in terms of identifying potential candidates for the physical origin of the interface defects. Very significant progress has been made in recent years in the passivation and intrinsic elimination of high-k/In0.53Ga0.47As interface defects to the point where genuine surface inversion for n and p type InGaAs MOS structures can be achieved and this research will be reviewed [4]. The characteristic signatures of capacitance and conductance, which indicate genuine surface inversion for an InGaAs MOS structure in inversion, will also be discussed [5]. While significant attention has been focussed on interface states and fixed charges in the InGaAs MOS system, the issue capacitance-voltage (CV) hysteresis has received relatively little attention to date [4]. This is now becoming a more pressing issue as progress is being made in controlling interface defect levels. Results will be presented covering CV hysteresis for the HfO2/InGaAs and Al2O3/InGaAs MOS structures with a range of high-k oxide thicknesses. The experimental results indicate that the defect states responsible for the hysteresis are located in the oxide transition region near the InGaAs/high-k interface and that engineering of this interface region, which contains native oxides of In, Ga and As, is the key to the control of CV hysteresis and accumulation frequency dispersion [7]. Finally, the presentation will cover the application of CV analysis to the understanding and quantification of charged defect components for InGaAs on insulator structures for 3D integration [8]. The authors acknowledge the financial support of Science Foundation Ireland through the INVENT project (SFI/09/IN.1/I2633) and the EU through the project COMPOSE3 (FP7-ICT- 2013-11-619325). [1] M. Radosavljevic et al., Tech.Dig.-Int. Electron Devices Meet, 126 (2010) [2] L. Czornomaz, et al., Tech.Dig.-Int. Electron Devices Meet. 6479088, (2012) [3] V. Djara, et al., Microelectronic Engineering 109 182–188 (2013) [4] N. Goel, D. et al., Tech. Dig. - Int. Electron Devices Meet. 363, (2008) [5] É. O’Connor, et al., Appl. Phys Lett 99, 212901 (2011) [6] Scott Monaghan, et al., IEEE Transaction on Electron Devices, 61, 4176 (2014) [7] Jun Lin, et al., J. Appl. Phys. 114, 144105 (2013) [8] K. Cherkaoui et al., Microelectronic Engineering 147 63–66 (2015)

L$_{\mathrm {g}} = 80$ -nm Trigate Quantum-Well In0.53Ga0.47As Metal–Oxide–Semiconductor Field-Effect Transistors With Al2O3/HfO2 Gate-Stack

We report on L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 80-nm trigate quantumwell InGaAs metal-oxide-semiconductor field-effect transistors (MOSFETs) with record combination of subthreshold swing, transconductance and ON-current performance. The device features a multilayer cap design, bilayer Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> (0.7/2 nm) gate-stack by atomic layer deposition and dry etched In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As fin. An L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">g</sub> = 80-nm trigate MOSFET with fin-width (W <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> ) = 30 nm and fin-height (H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fin</sub> ) = 20 nm exhibits excellent performance, such as ON-resistance (RON) = 220 Ω-μm, subthreshold swing (S) = 82 mV/dec, and drain-induced-barrier lowering = 10 mV/V at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V. Besides, the device exhibits record values of maximum transconductance (g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m_max</sub> ) = 1800 μS/μm and I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">ON</sub> = 0.41 mA/μm at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V, and a record combination of g <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m_max</sub> and S in any III-V nonplanar MOSFET technology.

III-V/Ge Device Engineering for CMOS Photonics

Heterogeneous integration of III-V compound semiconductors and Ge on the Si platform is one of the promising technologies for enhancing the performance of metal-oxide-semiconductor field effect transistors (MOSFETs) beyond the 10-nm technology node because of their high carrier mobilities. In addition, the III-Vs and Ge are also promising materials for photonic devices. Thus, we have investigated III-V/Ge device engineering for CMOS photonics, enabling monolithic integration of high-performance III-V/Ge CMOS transistors and III-V/Ge photonics on Si. The direct wafer bonding of III-V on Si has been investigated to form III-V on Insulator for III-V CMOS photonics. Extremely-thin-body InGaAs MOSFETs with the gate length of approximately 55 nm have successfully been demonstrated by using the wafer bonding. InP-based photonic-wire waveguide devices including micro bends, arrayed waveguide gratings, grating couplers, optical switches, and InGaAs photodetectors have also been demonstrated on the III-V-OI wafer. The gate stack formation on Ge is one of the critical issues for Ge MOSFETs. Recently, we have successfully demonstrated high-quality GeOx/Ge MOS interfaces formed by thermal oxidation and plasma oxidation. High-performance Ge pMOSFET and nMOSFET with thin EOT have been obtained using the GeOx/Ge MOS interfaces. We have also demonstrated that GeOx surface passivation is effective to reduce the dark current of Ge photodetectors in conjunction with gas-phase doped junction. We have also investigated strained SiGe optical modulators. We expect that compressive strain in SiGe enhances modulation efficiency, and an extremely small VπL of 0.033 V-cm is predicted. III-V/Ge heterogeneous integration is one of the promising ways for achieving ultrahigh performance electronic-photonic integrated circuits.

Toward Conformal Damage-Free Doping With Abrupt Ultrashallow Junction: Formation of Si Monolayers and Laser Anneal as a Novel Doping Technique for InGaAs nMOSFETs

New doping techniques are needed for the formation of abrupt, ultrashallow junctions with high doping concentration in the source/drain or source/drain extension regions of metal-oxide-semiconductor field-effect transistors (MOSFETs) at advanced technology nodes. In addition, 3-D device structures, such as fin field-effect transistors, require a good doping conformality. In this paper, the formation of monolayers of silicon on InGaAs by disilane or silane treatment of the InGaAs surface is studied as a conformal dopant source that does not introduce ion implant damage into the InGaAs, and laser anneal is used to drive in and activate the dopants to form an ultrashallow and very abrupt n++-junction. This novel doping technique is first demonstrated in planar InGaAs MOSFETs.

Self-Aligned and Non-Self-Aligned Contact Metallization in InGaAs Metal–Oxide-Semiconductor Field-Effect Transistors: A Simulation Study

2-D simulations were performed to compare the drive currents of In <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.53</sub> Ga <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0.47</sub> As n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) with self-aligned contact metallization and those with non-self-aligned contact metallization in order to determine the importance of self-aligned contact metallization in InGaAs MOSFETs at advanced technology nodes. A gate length of 15 nm was simulated, and various gap sizes between the via and the gate and various contact resistivities between the contact and the source/drain (S/D) were investigated. While very small gap sizes can significantly lower the S/D resistance for non-self-aligned contact metallization by bringing the via very close to the gate, an important benefit is still provided by self-aligned contact metallization in terms of contact area, allowing self-aligned contact metallization to outperform non-self-aligned contact metallization for the same contact resistivity, down to very low contact resistivity in the order of 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-9</sup> Ω·cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Impact of Fermi level pinning inside conduction band on electron mobility in InGaAs metal-oxide-semiconductor field-effect transistors

Combining the split capacitance-voltage method with Hall measurements revealed the existence of interface traps within the conduction band (CB) of InGaAs in metal-oxide-semiconductor (MOS) structures with Al2O3 (or HfO2)/InGaAs interfaces. The impact of these interface traps on inversion-layer mobilities in InGaAs MOS field-effect transistors with various interface structures was investigated. We found that the interface traps (&amp;gt;1013 cm−2 eV−1) induce Fermi level pining at an energy level 0.21–0.35 eV above the CB minimum, which degrades the mobilities in the high inversion carrier concentration region. Furthermore, the energy levels are tunable by changing the interface structures.

Investigation of Pd–InGaAs for the formation of self-aligned source/drain contacts in InGaAs metal–oxide–semiconductor field-effect transistors

The formation of salicide-like source/drain contacts on III–V MOSFETs necessitates a search for suitable metals that can react with III–V materials to form ohmic contacts with low sheet resistance and contact resistivity. To advance this search, the reaction between Pd and In0.53Ga0.47As is explored in this work. Reaction temperatures ranging from 200 to 400°C were investigated, and extensive physical and electrical characterization was performed. Pd completely reacts with In0.53Ga0.47As after annealing at temperatures as low as 200°C for 60 s to form a very smooth and uniform Pd–InGaAs film with good interfacial quality. Pd–InGaAs formed at 250°C was found to have a work function of ∼4.6±0.1eV, sheet resistance of ∼77.3Ω/square for a thickness of 20nm, and contact resistivity of ∼8.35×10−5Ωcm2 on In0.53Ga0.47As with n-type active doping concentration of ∼2×1018cm−3. With further development, Pd–InGaAs could potentially be useful as self-aligned contacts for InGaAs transistors.

Effects of forming gas anneal on ultrathin InGaAs nanowire metal-oxide-semiconductor field-effect transistors

InGaAs gate-all-around metal-oxide-semiconductor field-effect transistors (MOSFETs) with 6 nm nanowire thickness have been experimentally demonstrated at sub-80 nm channel length. The effects of forming gas anneal (FGA) on the performance of these devices have been systematically studied. The 30 min 400 °C FGA (4% H2/96% N2) is found to improve the quality of the Al2O3/InGaAs interface, resulting in a subthreshold slope reduction over 20 mV/dec (from 117 mV/dec in average to 93 mV/dec). Moreover, the improvement of interface quality also has positive impact on the on-state device performance. A scaling metrics study has been carried out for FGA treated devices with channel lengths down to 20 nm, indicating excellent gate electrostatic control. With the FGA passivation and the ultra-thin nanowire structure, InGaAs MOSFETs are promising for future logic applications.

A High-Frequency Transconductance Method for Characterization of High- $\kappa$ Border Traps in III-V MOSFETs

A novel method that reveals the spatial distribution of border traps in III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) is presented. The increase in transconductance with frequency is explored in a very wide frequency range (1 Hz-70 GHz) and a distributed RC network is used to model the oxide and trap capacitances. An evaluation of vertical InAs nanowire MOSFETs and surface-channel InGaAs MOSFETs with Al <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> O <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> /HfO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> high-κ gate dielectric shows a deep border-trap density of about 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">20</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> and a near-interfacial trap density of about 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sup> cm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> eV <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> . The latter causes an almost steplike increase in transconductance at 1-10 GHz. This demonstrates the importance of high-frequency characterization of high-κ dielectrics in III-V MOSFETs.

Strained In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors with epitaxial based biaxial strain

We have demonstrated epitaxial-based biaxially strained In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs). Tensile strained In0.53Ga0.47As MOSFETs shows a high peak mobility of 2150 cm2/Vs with the enhancement factor of 3.7 against Si MOSFETs. Furthermore, we have investigated the mobility enhancement mechanisms in the tensile strained In0.53Ga0.47As MOSFETs. It has been found that biaxial tensile strain is effective to enhance the electron mobility in InGaAs MOSFETs by an increase of inversion carrier density, which is caused by the modulation of conduction band minimum.

CMOS compatible self-aligned S/D regions for implant-free InGaAs MOSFETs

CMOS compatible self-aligned access regions for indium gallium arsenide (In0.53Ga0.47As) implant-free n-type metal–oxide–semiconductor field effect transistors (MOSFETs) are investigated. In situ doped n+ source/drain regions are selectively grown by metal-organic vapor phase epitaxy and self-aligned Nickel–InGaAs alloyed metal contacts are obtained using a self-aligned silicide-like process, where different process conditions are studied. Soft pre-epitaxy cleaning is followed by X-ray photoelectron spectroscopy, while the Ni–InGaAs/III–V interface is characterized by back-side SIMS profiling. Relevant contact and sheet resistances are measured and integration issues are highlighted. Gate-first implant-free self-aligned n-MOSFETs are produced to quantify the impact of Ni–InGaAs contacts on the device performance.

(Invited) High-K Dielectrics / High-Mobility Channel MOSFETs

We have systematically investigated the effect of process annealing sequence, channel thickness/doping concentration and high-k gate stacks on device performance of surface channel InGaAs metal-oxide-semiconductor field-effect-transistors (MOSFETs). In this paper, high performance InGaAs MOSFETs and tunneling field-effect-transistors (TFETs) with optimized device structure and process are presented.

Investigation of Surface Channel InGaAs MOSFETs with Al2O3 and ZrO2 ALD Gate Dielectric

This paper studies In0.53Ga0.47As and In0.7Ga0.3As surface channel metal-oxide-semiconductor field-effect-transistors (MOSFETs) with atomic layer deposition (ALD) of Al2O3 and ZrO2. This work systematically compared performance of InGaAs channel device with different Indium percentage. This includes drain current, transconductance, subthreshold swing, interface trap density and reliability. For both oxide systems, In0.53Ga0.47As channel MOSFETs show better subthreshold swing (125mV/dec versus 160mV/dec for Al2O3 EOT=4.4nm) and higher transconductance than In0.7Ga0.3As channel MOSFETs. Interface trap density measured by conductance method (1.08×1012 eV-1cm-2 versus 3.24×1012 eV-1cm-2 for Al2O3) also suggests that interface between In0.53Ga0.47As substrate and Al2O3 (or ZrO2) high-k dielectric is better than that of In0.7Ga0.3As.

Dc and rf characteristics of self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors using molecular beam epitaxy-Al2O3/Ga2O3(Gd2O3) as gate dielectrics

dc and rf characteristics of self-aligned inversion-channel In0.53Ga0.47As metal-oxide-semiconductor field-effect transistors (MOSFETs) using molecular beam epitaxy (MBE) deposited Al2O3/Ga2O3(Gd2O3) (GGO) high κ dielectrics and TiN metal gates are reported. MOSFETs with various oxide thicknesses were fabricated. The In0.53Ga0.47As MOSFETs using Al2O3(2 nm)/GGO (5 nm) gate dielectric demonstrated a maximum drain current of 1.05 mA/μm and a peak transconductance of 714 μS/μm, both are the highest values ever reported for enhancement-mode InGaAs MOSFETs with 1 μm gate length. In addition, the same transistors exhibited excellent embedded rf properties and achieved a fT of 17.9 GHz and a fmax of 12.1 GHz. The high-quality in situ MBE growth of high κ dielectrics/InGaAs has attributed to the high device performance.

High Performance InGaAs MOSFETs with High Mobility using InP Barrier Layer

We have fabricated In0.7Ga0.3As and In0.53Ga0.47As metal-oxide-semiconductor field-effect-transistors (MOSFETs) with and without InP barrier layer using atomic layer deposited (ALD) Al2O3 gate oxide directly on III-V substrates. InP is an excellent barrier and passivation layer to enhance current driving capability for these devices, especially for In0.7Ga0.3As MOSFETs due to good conduction band offsets. In0.7Ga0.3As MOSFETs with InP barrier layer show much higher transconductance and lower subthreshold swing than other MOSFETs in our study, and exhibit high drive current of 98 mA/mm (L=20 um), subthreshold swing of 106 mV/dec and maximum effective channel mobility of 4402 cm2/Vs, which is amongst the highest reported in the literature.