InGaAs High Electron Mobility Transistors Research Articles

Optimized recess etching criteria for T‐gate fabrication achieving ft = 290 GHz at Lg = 124 nm in metamorphic high electron mobility transistor with In0.7Ga0.3As channel

AbstractThe authors propose criteria for recess etching to fabricate T‐gate used in InGaAs high electron mobility transistors (HEMTs). By patterning additional rectangular pads on the source and drain metals in the e‐beam lithography step, it is possible to measure the drain‐to‐source resistance (Rds) and current (Ids). The ratio (Γ) of before and after etching for each Rds and Ids can be used as criteria to determine the point in time to stop etching. By performing recess etching with Γ= 1.97 for Rds and Γ= 0.38 for Ids on an epiwafer having cap doping concentration of 2 × 1019 cm−3 and channel indium content of 0.7, the authors have fabricated InGaAs metamorphic high electron mobility transistor (mHEMT) device showing gm,max= 1603 mS/mm and ft= 290 GHz at Lg= 124 nm. The criteria presented can be applied to InGaAs HEMTs with various epitaxial structures.

A New Analytical Large-Signal Model for Quasi-Ballistic Transport in InGaAs HEMTs Accommodating Dislocation Scattering

A surface-potential-based analytical large-signal model, which is applicable to both ballistic and quasi-ballistic transport in InGaAs high electron mobility transistors, is developed. Based on the one-flux method and a new transmission coefficient, a new two-dimensional electron gas charge density is derived, while the dislocation scattering is novelly taken into account. Then, a unified expression for Ef valid in all the regions of gate voltages is determined, which is utilized to directly calculate the surface potential. The flux is used to derive the drain current model incorporating important physical effects. Moreover, the gate-source capacitance Cgs and gate-drain capacitance Cgd are obtained analytically. The model is extensively validated with the numerical simulations and measured data of the InGaAs HEMT device with the gate length of 100 nm. The model is in excellent agreement with the measurements under I-V, C-V, small-signal conditions, and large-signal conditions.

Heterogeneous and Monolithic 3D Integration Technology for Mixed-Signal ICs

For next-generation system-on-chips (SoCs) in diverse applications (RF, sensor, display, etc.) which require high-performance, small form factors, and low power consumption, heterogeneous and monolithic 3D (M3D) integration employing advanced Si CMOS technology has been intriguing. To realize the M3D-based systems, it is important to take into account the relationship between the top and bottom devices in terms of thermal budget, electrical coupling, and operability when using different materials and various processes during integration and sequential fabrication. In this paper, from this perspective, we present our recent progress of III-V devices on Si bottom devices/circuits for providing informative guidelines in RF and imaging devices. Successful fabrication of the high-performance InGaAs high electron mobility transistors (HEMTs) on the bottom ICs, with a high unity current gain cutoff frequency (fT) and unity power gain cutoff frequency (fMAX) was accomplished without substrate noise. Furthermore, the insertion of an intermediate metal plate between the top and bottom devices reduced the thermal interaction. Furthermore, the InGaAs photodetectors (PDs) were monolithically integrated on Si bottom devices without thermal damage due to low process temperature. Based on the integrated devices, we successfully evaluated the device scalability using sequential fabrication and basic readout functions of integrated circuits.

Heterogeneous and Monolithic 3D Integration of III-V-Based Radio Frequency Devices on Si CMOS Circuits.

Next-generation wireless communication such as sixth-generation (6G) and beyond is expected to require high-frequency, multifunctionality, and power-efficiency systems. A III-V compound semiconductor is a promising technology for high-frequency applications, and a Si complementary metal-oxide-semiconductor (CMOS) is the never-beaten technology for highly integrated digital circuits. To harness the advantages of these two technologies, monolithic integration of III-V and Si electronics is beneficial, so that there have been everlasting efforts to accomplish the monolithic integration. Considering that the on horizon 6G wireless communication requires faster and more energy-efficient system-on-chip technologies, it is imperative to realize a radio frequency (RF) system in which III-V technology and Si CMOS technology are integrated at a device level. Here we report heterogeneous and monolithic three-dimensional (3D) analog/RF-digital mixed-signal integrated circuits that contain two types of InGaAs high-electron-mobility transistors (HEMTs) designed for high fT and fMAX in the top and Si CMOS mixed-signal circuits consisting of an analog-to-digital converter and digital-to-analog converter in the bottom. A high unity current gain cutoff frequency of 448 GHz and unity power gain cutoff frequency of 742 GHz have been achieved by the fT oriented and fMAX oriented InGaAs HEMTs, respectively, without being affected by mixed-signal interference. At the same time, the bottom Si CMOS circuits provide valid signals without any performance degradation by the integration process.

Microwave Frequency Tripler using InGaAs HEMT Transistor

In this work, a 3x frequency multiplier in microstrip technology is presented. The frequency multiplier is used to generate 17.4GHz signal by multiplying 5.8GHz input and by using Indium gallium arsenide (InGaAs) High Electron Mobility Transistor (MGF4918D). The input and output reflection coefficients (S11 and S22) are less than -30 dB. The Rollet factor is greater than unity at the fundamental frequency 5.8GHz and in the 3rd harmonic which places at the frequency of 17.4GHz. The maximum conversion of the fundamental signal to the 3rd harmonic is given by an input power of 3.6dBm, gate-source voltage of -0.6V and drain-source voltage of 3V. The dissipated power Pdc is 45 mW and the surface of the chip occupied on a FR- 4 substrate is 7.3 x 3 cm2.

HOLE ACCUMULATION EFFECT OF InGaAs HIGH-ELECTRON-MOBILITY TRANSISTORS WITH A 1550-nm WAVELENGTH FEMTOSECOND PULSE LASER

InGaAs is known as a material system with high electron mobility derived from InAs and can be formed by metal organic chemical vapor deposition. The base material substrate is InP and is formed by controlling the composition ratio of In and Ga to lattice match with this InP. The bandgap energy Eg of InGaAs is 0.87 eV, and photoelectric conversion of 1550-nm light, which is a communication wavelength band, can be executed. Therefore, it is now used as a detector material in optical communication technology. In this study, we investigated the photoresponsive properties of InGaAs high-electron-mobility transistors (HEMTs) with simultaneous utilization of photoresponse characteristics and high-frequency response characteristics of this InGaAs crystal. A1550-nm wavelength femtosecond pulse laser (with a pulse width of 100 fs and a period of 50 MHz) was coupled with DC light with a wavelength of 1480 nm and irradiated from the InGaAs HEMT metal electrode surface. Laser light transmitted through the side of the gate metal electrode into the device structure generates electron-hole pairs via the photoelectric effect in the InGaAs layer, and it was confirmed that the maximum drain current of 0.4 mA was reduced. A current response is detected inside the semiconductor by transporting electrons to the drain electrode side and holes to the source electrode side. Because the laser used is pulsed light, the process of generation and disappearance of electron-hole pairs were confirmed as photoresponsive properties.

MOCVD Growth of High Quality InGaAs HEMT Layers on Large Scale Si Wafers for Heterogeneous Integration With Si CMOS

We report on the growth of In0.30Ga0.70As channel high electron mobility transistor (HEMT) epi-layers on a 200-mm Si substrate by metal-organic-chemical-vapor-deposition. The HEMT layers were grown on the Si substrate by using a ~3- ${\mu }\text{m}$ thick epitaxial buffer composing of a Ge layer, a GaAs layer, and a compositionally graded and strain relaxed InAlAs layer. The optimized epitaxy has a threading dislocation density of less than $2 {\times } 10^{{7}}$ cm−2 and a root mean square surface roughness of ~6.7 nm. The device active layers include a ${ {\delta } }$ -doped InAlAs bottom barrier, a ~15-nm thick InGaAs channel, a ~8-nm InGaP top barrier layer and a heavily doped InGaAs contact layer. MOSHEMTs with channel length down to 130 nm were fabricated. The devices achieve a peak transconductance of ${\sim }450 ~{\mu }\text{S}/ {\mu }\text{m}$ at ${V} _{ D}$ of 0.5 V. The peak effective mobility ( ${\mu }_{\text {eff}}$ ) in a device with a channel length of 20 $ {\mu }\text{m}$ device channel was ~3700 cm2/ $\text{V} {\cdot }\text{s}$ .

Numerical Analysis of Terahertz Emissions From an Ungated HEMT Using Full-Wave Hydrodynamic Model

In this paper, we show how plasma-wave instability in an asymmetrically biased ungated InGaAs high-electron mobility transistor (HEMT) leads to terahertz emissions. Numerical calculations are provided using a new Maxwell-hydrodynamic solver. Using this solver, an accurate plasma-wave model is presented, accounting for nonuniform surroundings and finite dimensions of the 2D electron gas (2DEG) layer within the HEMT. We estimate that hundreds of nanowatts of power can be expected from such devices under ideal boundary conditions and sufficient channel mobility. Effects due to variations of carrier velocity, carrier concentration, and 2DEG confinement on the emitted power levels are also considered to provide design guidelines.

(Invited) Advanced CMOS Device Technologies Discussed Also with Transition-Metal Di-Chalcogenide (TMDC) Channel

Advanced CMOS device technology for a high-performance system-on-a-chip (SoC) LSI is firstly discussed by using benchmarking of published data [1-6], mainly-highlighted by a FinFET and beyond, as shown in Fig. 1. To enhance the performance of FinFET devices, a low-voltage operation less than 0.7 V with smaller variability of characteristics is highly required rather than an enlargement of channel width (Weff / Wfootprint). Here, Weff and Wfootprint mean effective and footprint channel widths. After that, higher-mobility channel devices are strongly needed with superimposed manner having an InGaAs high-electron mobility transistor (HEMT), InGaAs quantum well (QW), InAs QW, and InGaAs MISFET having an appropriate smaller bandgap. In this case, smooth thin-channel is promising to suppress the variability of characteristics. Therefore, an atomically-consistent semiconductor material such as a graphene and transition-metal di-chalcogenide (TMDC) are favorable candidates. Although the graphene has a zero band-gap, the TMDCs have superior properties such as an appropriate bandgap, for example, 1.2 eV in single-layer MoS2 film. Furthermore, they also yield higher mobility, transparent and mechanical robustness. In our experiments, a higher Hall mobility of electron with 28 cm2/Vs in 10-nm-thick MoS2 film is achieved even by using a magnetron sputtering process with MoS2 target for channel formation [7]. This might be caused by a suppression of carrier scattering due to contaminations such as alkali metals of sodium and potassium, impurities, crystal defects, and film roughness in the MoS2 film. In conclusion, the TMDC-channel MISFET could be suitable for high-performance SoC LSIs as not only advanced CMOS devices but also monolithic transistor to enhance the functionalities per chip area. Furthermore, it has a strong possibility achieving not only more-Moore and more-than-Moore but also more-comfort properties for high-performance human-interface (I/F) devices such as a transparent and flexible display. Acknowledgements This work was partially supported by JSPS Grant-in-Aid for Scientific Research on Innovative Areas: Grant Number 26105014, and the Center of Innovation Program from Japan Science and Technology Agency, JST.

TeraHertz electronic noise in field-effect transistors

We present a theoretical investigation of high-frequency electronic noise in field-effect transistors used as detectors of TeraHertz radiation. Calculations are performed using the hydrodynamic-Langevin approach and specialized to the case of InGaAs high-electron mobility transistors. The main physical phenomena associated with the effect of branching of the total current between channel and gate and the appearance of two-dimensional plasma waves are discussed. We demonstrate that thermally excited standing plasma waves originate series of resonant peaks in the corresponding noise spectral densities whose presence can be controlled by the embedding circuit. A significant damping of the high-frequency excess noise is found when the transistor is submitted to a two-lasers optical photo-excitation presenting a beating frequency in the TeraHertz range. Finally, we discuss the dependence of the damping effect, as well as a shift of the resonance peaks from the presence of channel ungated regions.

Impact of T-gate stem height on parasitic gate delay time in InGaAs-HEMTs

The impact of the stem height of T-gate electrodes on the parasitic gate delay time in InGaAs high electron mobility transistors (HEMTs) is studied. Since T-gates with higher stem height make the parasitic gate capacitance smaller, the higher stem height is expected to minimize the parasitic gate delay. However, a systematic study using the devices with different stem height of T-gates reveals that the parasitic gate delay time decreases with the parasitic gate capacitance only at a drain voltage around the knee voltage and it becomes less sensitive to the parasitic capacitance by the T-gate when the device is operated in the deep saturation region at high drain bias voltage. This result suggests a design strategy for T-gate electrodes so that the tradeoff between the gate resistance and gate capacitance must be considered seriously in the devices for low-voltage applications, while one has more flexibility to use the T-gate electrode with a large head in the devices for high-voltage applications.

Nonlinear photoresponse of field effect transistors terahertz detectors at high irradiation intensities

Terahertz power dependence of the photoresponse of field effect transistors, operating at frequencies from 0.1 to 3 THz for incident radiation power density up to 100 kW/cm2 was studied for Si metal–oxide–semiconductor field-effect transistors and InGaAs high electron mobility transistors. The photoresponse increased linearly with increasing radiation intensity up to the kW/cm2 range. Nonlinearity followed by saturation of the photoresponse was observed for all investigated field effect transistors for intensities above several kW/cm2. The observed photoresponse nonlinearity is explained by nonlinearity and saturation of the transistor channel current. A theoretical model of terahertz field effect transistor photoresponse at high intensity was developed. The model explains quantitative experimental data both in linear and nonlinear regions. Our results show that dynamic range of field effect transistors is very high and can extend over more than six orders of magnitudes of power densities (from ∼0.5 mW/cm2 to ∼5 kW/cm2).

Theory and measurement of plasmonic terahertz detector response to large signals

Electron gas in the conduction channel of a Field Effect Transistor (FET) can support collective plasma oscillations tunable by the gate voltage. In the Dyakonov-Shur terahertz (THz) detector, nonlinearities in the plasma wave propagation in the gated channel of a FET lead to a constant source-to-drain voltage providing the detector output. We present the detector theory in the frame of the hydrodynamic model using the electron plasma Navier-Stokes and thermal transport equations, thus fully accounting for the hydrodynamic non-linearity, the viscosity, and pressure gradients in the detector response. Both resonant and broadband operations of the high electron mobility transistor (HEMT) based plasmonic detectors are described by this model. The relation between the electron channel density and gate voltage was modeled by the unified charge control model applicable both above and below the threshold voltage. The theoretical results are compared with the response measured in the short channel InGaAs HEMT and the analytical approximation. The THz source was operating at 1.63 THz, and the response was measured at varying signal intensities. The response of the detector operated in the open drain mode was measured above and below the threshold, and the theoretical and experimental results are shown to be in good agreement.

InGaAs HEMTs with T‐gate electrodes formed by multi‐layer SiCN molds

AbstractWe report a method to control the shape of T‐gates precisely by using multi‐layer SiCN molds. The SiCN molds consist of a series of SiCN thin films with gradually changed etching properties. The SiCN was deposited by plasma‐enhanced chemical vapor deposition using hexamethyldisilazane (HMDS) vapor. An optimized deposition condition of SiCN molds enables us to achieve more precisely control in the T‐gate shape such as the stem angle. The SiCN molds technique was applied to the fabrication of T‐gates in InGaAs high electron mobility transistors (HEMTs). Two types of HEMTs using the SiCN molds with different deposition conditions were fabricated. The detail analysis of the HEMTs indicates that the difference in the parasitic gate delay and gate resistance reflects the T‐gate shapes. (© 2013 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

1.0 μm gate-length InP-based InGaAs high electron mobility transistors by mental organic chemical vapor deposition

InGaAs high electron mobility transistors (HEMTs) on InP substrate with very good device performance have been grown by mental organic chemical vapor deposition (MOCVD). Room temperature Hall mobilities of the 2-DEG are measured to be over 8 700 cm2/V-s with sheet carrier densities larger than 4.6×1012 cm−2. Transistors with 1.0 μm gate length exhibits transconductance up to 842 mS/mm. Excellent depletion-mode operation, with a threshold voltage of −0.3 V and IDSS of 673 mA/mm, is realized. The non-alloyed ohmic contact special resistance is as low as 1.66×10−8 Ω/cm2, which is so far the lowest ohmic contact special resistance. The unity current gain cut off frequency (fT) and the maximum oscillation frequency (fmax) are 42.7 and 61.3 GHz, respectively. These results are very encouraging toward manufacturing InP-based HEMT by MOCVD.

Impact of Effective Mass on the Scaling Behavior of the $f_{T}$ and $f_{\bf max}$ of III–V High-Electron-Mobility Transistors

Among the contenders for applications at terahertz frequencies are III-V high-electron-mobility transistors (HEMTs). In this paper, we report on a tendency for III-V devices with low effective-mass channel materials to exhibit a saturation in their unity-current-gain and unity-power-gain cutoff frequencies (fT and fmax) with a downscaling of gate length. We focus on InGaAs and GaN HEMTs and examine gate lengths from 50 nm down to 10 nm. A self-consistent, quantum-mechanical solver based on the method of nonequilibrium Green's functions is used to quasistatically extract the fT for intrinsic III-V devices. This model is then combined with the series resistances of the heterostructure stack and the parasitic resistances and capacitances of the metal contacts to develop a complete extrinsic model, and to extract the extrinsic fT and fmax. It is shown that the fT and fmax of III-V devices will saturate, i.e., attain a maximum value that ceases to increase as the gate length is scaled down, and that the saturation is caused by the low effective mass of III-V materials. It is also shown that the InGaAs HEMTs have faster fT at long gate lengths, but as a consequence of their lower effective mass, they experience a more rapid fT saturation than the GaN HEMTs, such that the two devices have a comparable fT at very short gate lengths (~10 nm). On the other hand, due to favorable parasitics, it is shown that the InGaAs HEMTs have a higher fmax at all the gate lengths considered in this paper.

Plasmonic terahertz detector response at high intensities

Recent work on plasmonic terahertz detection using field effect transistors (FETs) has yielded detectors with high responsivity. Therefore, deviation from small signal mode of operation, when the detector signal is simply proportional to the THz intensity, must be considered. This work presents a new analytical model to predict terahertz response in a FET at arbitrary intensity levels. The proposed analytical model was experimentally validated using a 0.13 μm InGaAs high electron mobility transistor and optically pumped CO2 gas laser operating at 1.63 THz of varying output intensities. The model is suitable for implementation in circuit simulators and might be used for device optimization and THz circuit design.

InGaAs HEMTs with T‐gate electrodes fabricated using HMDS SiN mold

AbstractWe report a method using SiN molds to controlling the shape of T‐gate electrodes. The SiN molds were constructed of multilayer SiN films with different etching properties. The SiN was deposited by plasma‐enhanced chemical vapor deposition using hexamethyldisilazane (HMDS) vapor. The SiN molds were used to fabricate T‐gate electrodes for InGaAs high electron mobility transistors (HEMTs). Two types of HEMTs were fabricated using the molds with different SiN layer structures. The gate delay analysis of the HEMTs showed that the difference in the parasitic gate delay reflects the shape of the T‐gate electrodes. (© 2012 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Impact of T‐gate electrode on gate capacitance in In0.7Ga0.3As HEMTs

AbstractThe intrinsic and parasitic gate capacitance of In0.7Ga0.3As‐channel high electron mobility transistors (HEMTs) are estimated by the gate delay analysis. We prepared 80‐nm InGaAs HEMTs with different geometry of T‐gate electrodes to discuss how the T‐gate electrode affects parasitic gate delay. The results indicate that the both of the top part and stem of the T‐gate electrode has an influence on the cutoff frequency of 80‐nm‐gate HEMTs and in total the parasitic gate delay caused by the T‐gate electrode is more than half of the total gate delay. (© 2011 WILEY‐VCH Verlag GmbH & Co. KGaA, Weinheim)

Impact of ⟨110⟩ uniaxial strain on n-channel In0.15Ga0.85As high electron mobility transistors

This letter reports on a study of the impact of ⟨110⟩ uniaxial strain on the characteristics of InGaAs high electron mobility transistors (HEMT) by bending GaAs chips up to a strain level of 0.4%. Systematic changes in the threshold voltage and intrinsic transconductance were observed. These changes can be well predicted by Schrödinger–Poisson simulations of the one-dimensional electrostatics of the device that include the piezoelectric effect, Schottky barrier height change, and sub-band quantization change due to strain. The effect of ⟨110⟩ strain on the device electrostatics emerges as a dominant effect over that of transport in the studied InGaAs HEMTs.