InGaAs Field Effect Transistors Research Articles

Terahertz Response of Tightly Concatenated Two Dimensional InGaAs Field-Effect Transistors Integrated on a Single Chip

THz response of AlGaAs/InGaAs/GaAs HEMT structure has been investigated. The structure consists of the serpentine chain of series connected HEMTs. The source of one is the drain for the subsequent transistor. Experiments have been showed THz response peculiarities of such structures and enhanced noise equivalent power.

Defect evaluation in InGaAs field effect transistors with HfO2 or Al2O3 dielectric

The performance of InGaAs metal oxide semiconductor field effect transistors with Al2O3 or HfO2 as gate oxide is evaluated and compared. The Al2O3 transistors show the lowest subthreshold slope and mid gap Dit, however, the HfO2 transistors reach a higher maximum transconductance (gmax) due to the higher oxide capacitance. Both high-κ dielectrics show a gm-frequency dispersion due to tunneling into border traps with a negligible activation energy as determined from temperature dependent measurements. The total amount of trapped charge at border traps is lower in the HfO2 devices. Scaling the HfO2 thickness further reduces the gm-frequency dispersion, possibly due to detrapping to the gate electrode.

Fabrication and Simulation of InGaAs Field-Effect Transistors with II–VI Tunneling Insulators

This study shows the use of a high-κ ZnS/ZnMgS/ZnS heteroepitaxial tunneling layer in an InGaAs field-effect transistor. Experimental fabrication and simulation of this semiconductor structure show promise of reducing threshold voltage variation by replacing silicon and hafnium oxides as a gate insulator. The II–VI tunneling insulator is grown on an InGaAs substrate using ultraviolet-irradiated metalorganic vapor-phase epitaxy. GeO x -Ge cladded quantum dots are self-assembled to form the gate material. The gate consists of two self-assembled individually cladded quantum dot layers which allow multilogic behavior. Simulations calculated by solving the Schrodinger and Poisson equations self-consistently confirm experimental I D–V D characteristics and show the electron distribution in an inversion channel/quantum well under different gate voltage bias values.

Detection of terahertz radiation by tightly concatenated InGaAs field-effect transistors integrated on a single chip

A tightly concatenated chain of InGaAs field-effect transistors with an asymmetric T-gate in each transistor demonstrates strong terahertz photovoltaic response without using supplementary antenna elements. We obtain the responsivity above 1000 V/W and up to 2000 V/W for unbiased and drain-biased transistors in the chain, respectively, with the noise equivalent power below 10−11 W/Hz0.5 in the unbiased mode of the detector operation.

Four-State Sub-12-nm FETs Employing Lattice-Matched II–VI Barrier Layers

Three-state behavior has been demonstrated in Si and InGaAs field-effect transistors (FETs) when two layers of cladded quantum dots (QDs), such as SiOx-cladded Si or GeOx-cladded Ge, are assembled on the thin tunnel gate insulator. This paper describes FET structures that have the potential to exhibit four states. These structures include: (1) quantum dot gate (QDG) FETs with dissimilar dot layers, (2) quantum dot channel (QDC) with and without QDG layers, (3) spatial wavefunction switched (SWS) FETs with multiple coupled quantum well channels, and (4) hybrid SWS–QDC structures having multiple drains/sources. Four-state FETs enable compact low-power novel multivalued logic and two-bit memory architectures. Furthermore, we show that the performance of these FETs can be enhanced by the incorporation of II–VI nearly lattice-matched layers in place of gate oxides and quantum well/dot barriers or claddings. Lattice-matched high-energy gap layers cause reduction in interface state density and control of threshold voltage variability, while providing a higher dielectric constant than SiO2. Simulations involving self-consistent solutions of the Poisson and Schrodinger equations, and transfer probability rate from channel (well or dot layer) to gate (QD layer) are used to design sub-12-nm FETs, which will aid the design of multibit logic and memory cells.

LOW FREQUENCY NOISE AND INTERFACE DENSITY OF TRAPS IN InGaAs MOSFETs WITH GdScO3 HIGH-K DIELECTRIC

Insulated gate n-channel enhancement mode InGaAs field effect transistors with the GdScO 3 high-k dielectric have been fabricated and studied. The low frequency noise was high indicating a high interface density of traps. Trap density and its dependence on the gate voltage have been extracted from the noise and conductance measurements.

Transconductance characteristics and plasma oscillations in nanometric InGaAs field effect transistors

AbstractBy Monte Carlo simulations we investigate the plasma spectrum in n-type InGaAs field effect transistors at 300K in the whole region of operating conditions from ohmic to saturation regime of the transconductance characteristics. The presence of a two dimensional (2D) plasma peak predicted within the gradual channel approximation is confirmed by the microscopic model and its properties are analyzed systematically. At the highest gate voltages the 2D peak is found to become practically independent of the channel width.

Terahertz response of InGaAs field effect transistors in quantizing magnetic fields

Terahertz (THz) detection by plasma wave mechanism in InGaAs field effect transistors is studied in high/quantizing magnetic fields regime. The correlation between the photovoltaic response and magnetoresistance is revealed. It allows explaining the dominant physical mechanism responsible for strong oscillations observed in the transistor THz photoresponse. The results indicate also a serious discrepancy between experimental data and existing theoretical model.

A Physics-Based Compact Model of III–V FETs for Digital Logic Applications: Current–Voltage and Capacitance–Voltage Characteristics

A physics-based analytical compact model of InGaAs field-effect transistors (FETs) for digital logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation while capturing the essential physics, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures short channel effects, trapezoidal-shape quantum-well energies, bias-dependent ballistic ratios, and capacitances including 2D potential profile information. Each is verified via numerical calculations and 2D electrostatic simulation, followed by a comparison of the model I-V characteristics with experiment data. Finally, the transient response of FO4 inverters demonstrates the use of the compact model for future technology circuit simulations.

AIGaAsSb Buffer/Barrier on GaAs substrate for InAs channel devices with high electron mobility and practical reliability

InAs/AlGaAsSb deep quantum well was successfully formed on GaAs substrate and examined for two electron devices, Hall elements (HEs), and field-effect transistors (FETs). With a thin buffer layer of 600 nm AIGaAsSb on GaAs substrate, we observed high electron mobility more than 23000 cm2/Vs and extrinsic effective electron velocity of 2.2 x 107 cm/s for a 15 nm thick InAs channel at room temperature. AIGaAsSb lattice matched to InAs was discussed from the view points of insulating property, carrier confinement, and oxidization rate. Reliability data good enough for practical use were also obtained for HEs. We demonstrated AIGaAsSb as a promising buffer/barrier layers for InAs channel devices on GaAs substrate, and we discussed the possible advantages of AIGaAsSb also for InGaAs FETs.

InGaAs field-effect transistors with submicron gates for K-band applications

Depletion mode InGaAs microwave power MISFETs with 0.7 mu m gate lengths and 0.2 mm gate widths have been fabricated using an epitaxial process. The devices employed a plasma deposited silicon dioxide gate insulator. The RF power performance at 18 GHz, 20 GHz, and 23 GHz is presented. An output power density of 1.04 W/mm with a corresponding power gain and power-added efficiency of 3.7 dB and 40%, respectively, was obtained at 18 GHz. This is the highest output power density obtained for an InGaAs based transistor on InP at K-band. Record output power densities for an InGaAs MISFET were also demonstrated to the stable within 3% over 17 hours of continuous operation at 18 GHz.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>