Induced Threshold Voltage Shift Research Articles

P‐13: Excessive Oxygen induced Threshold Voltage Shifts in High Mobility Top‐Gate PrIZO TFTs

The top gate self‐alignment (TGSA) Praseodymium‐doped indium zinc oxide (PrIZO) thin film transistor (TFT) was fabricated with different process condition in our production line, and high field effect mobility of 40.83 cm2 V‐1 s‐1 was obtained by regulating the GI and ILD parameters. At the same time, the devices show excellent stability with PBTS of 0.52 V and NBTIS of ‐0.9 V, indicating its potential in overcoming the trade‐off between mobility and reliability.

Impact of hole trap-detrap mechanism on X-ray irradiation induced threshold voltage shift of radiation-hardened GAA TFET device

We demonstrate the X-ray irradiation effect on a radiation-hardened gate-all-around tunnel FET (GAA TFET) device. The radiation-hardened device has a high and fixed oxide electric field, which is responsible to attain equilibrium state of the device. Once the device reaches equilibrium, the threshold voltage starts to saturate for any variation in the gate bias. Therefore, the fixed electric field in the oxide region is reduced with the application of negative bias to the gate, which varies the equilibrium trapped charge concentration in the oxide. The negative gate bias causes electrons of oxide and holes from the bias terminal to recombine, which ultimately reduces the electric field in the oxide region. This variation in charge concentration results in a new threshold voltage when the device has been re-irradiated. Further, the unique carrier injection mechanism of the TFET device plays a significant role in trapping and detrapping mechanisms along the channel. The report consists of positive charge trapping and detrapping of charge carriers along the channel of the GAA-TFET device. In addition, the report also deals with the impact of applying excessive gate bias to the device and its impact on electric fields. For the X-ray irradiation analysis, several figures of merit are taken into consideration before coming to the conclusion of the report, such as geminate yield, trapped charges in the oxide region, and time-varying positive charge build-up in the oxide. The device under consideration has also been irradiated with several radiation doses and time durations to verify its robustness.

Investigation of Thermally Induced Threshold Voltage Shift in Normally-OFF p-GaN Gate HEMTs

In this article, the thermally induced threshold voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{TH}}$ </tex-math></inline-formula> ) shift was investigated on two types of normally- OFF p-GaN gate high-electron-mobility transistors (HEMTs), featuring either an Ohmic-type or a Schottky-type gate. A positive <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{TH}}$ </tex-math></inline-formula> shift in a Schottky-type device and a negative <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{TH}}$ </tex-math></inline-formula> shift in an Ohmic-type device were observed at elevated temperatures. Temperature-dependent gate current–voltage ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}-{V}$ </tex-math></inline-formula> ) and the transfer-length-method (TLM) analysis revealed that the bias condition across the p-GaN/AlGaN/GaN heterostructures was changed in both Schottky- and Ohmic-type devices as temperature increased. We propose that: 1) temperature-enhanced hole injection through thermionic emission which lowers the knee voltage of the Ohmic-metal/ p-GaN contact in Ohmic-type devices and 2) thermally enhanced gate current which enlarges the bias voltage across the Schottky-metal/p-GaN junction in Schottky-type devices, resulted in the observed <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${V}_{\text{TH}}$ </tex-math></inline-formula> instability characteristics. The photoluminescence measurements were conducted to verify the thermally-enhanced ionization of magnesium dopants in the p-GaN and the corresponding instability issues.

Conduction band offset-dependent induced threshold voltage shifts in a-InGaZnO TFTs under positive bias illumination stress

In this paper, the dependence of threshold voltage (Vth) changes to amorphous-indium gallium zinc oxide (a-IGZO) thin film transistors (TFTs) under positive bias light illumination (PBIS) on the height of the conduction band offset was studied. Using SiO2, HfO2, and Al2O3 as gate dielectrics, three different types of a-IGZO TFTs were used in the experiment. Electrical parameters and the density of states of each TFT were measured. Of the devices studied, the interface characteristics between the a-IGZO and the gate dielectric were the best using SiO2 and the worst using Al2O3. HfO2 had the smallest conduction band offsets (CBO) of 2.26 eV. We also performed PBS and PBIS evaluation to confirm the stability of TFTs. The Vth shift in the three samples was insignificant under PBS, but the Vth shifts occurred under PBIS in the order of HfO2, Al2O3, and SiO2. The interfacial characteristics of a-IGZO and the dielectric did not change after PBIS in all three devices; the lower the CBO height, the greater the Vth shift after PBIS. The predominant cause of the Vth shift under PBIS is the accumulation of injected photoelectrons that have sufficient energy to tunnel the CBO barrier into the gate dielectric by positive gate bias.

Optically Controlled Ternary Logic Circuits Based on Organic Antiambipolar Transistors

AbstractA ternary inverter is demonstrated based on an organic antiambipolar transistor (AAT), in which the output logic states can be precisely controlled with appropriate optical signals. First, the photoresponse of AATs consisting of PTCDI‐C8 and α‐6T layers is systematically investigated. Under visible light, the Λ‐shaped transfer curve of the AATs undergoes a noticeable broadening due to the optically induced threshold voltage shift in both the PTCDI‐C8 and α‐6T controlled ranges. Under ultraviolet light, broadening is observed only on the α‐6T side. These contrasting impacts of the two light signals enable to tune the balance of the ternary logic states in the inverters, including the output voltage levels and the ratio of the respective logic states. Such optically controlled ternary logic circuits possess great potential for their application in next‐generation optoelectronic devices.

Annealing atmosphere-dependent electrical characteristics and bias stability of N-doped InZnSnO thin film transistors

The dependence of electrical characteristics and gate bias stress stability of N-doped InZnSnO (IZTO:N) thin film transistors (TFTs) on annealing atmosphere was investigated. The annealing process was performed in air, O2 and N2, respectively, after the deposition of IZTO:N thin film by magnetron sputtering. All annealed IZTO:N films are amorphous and show a high transmittance in the visible light range. The N2-annealed TFT has the highest saturation mobility (μSAT) of 39.5 cm2 V−1s−1 and the lowest subthreshold swing (SS) of 0.40 V/decade. The air-annealed TFT shows similar mobility and SS to the N2-annealed TFT while the O2-annealed TFT shows the lowest mobility and the largest SS. We found that annealing atmosphere has impact on the bias stress stability of the TFTs. Bias stress induced threshold voltage shift of the O2-annealed TFTs is reduced compared to that of air-annealed and N2-annealed TFTs due to the decrease in oxygen vacancy.

Bias temperature instability and condition monitoring in SiC power MOSFETs

Threshold voltage shift due to bias temperature instability (BTI) is a major concern in SiC power MOSFETs. The SiC/SiO2 gate dielectric interface is typically characterized by a higher density of interface traps compared to the conventional Si/SiO2 interface. The threshold voltage shift that arises from BTI has significant implications on the reliability of SiC power MOSFETs, hence, techniques for detecting the change in electrical parameters due to gate oxide degradation are desirable. Using accelerated high temperature gate bias stress tests on SiC MOSFETs, it has been shown that the output and transfer characteristics are affected by BTI. This paper presents the impact BTI induced threshold voltage shift on the forward voltage of the SiC MOSFET body diode during third quadrant operation. Using the forward voltage of the body diode during reverse conduction of low currents, threshold voltage shift can be detected, hence, the impact of BTI can be evaluated. The implications of the body diode forward voltage shift on junction temperature measurements are also studied in the context of TSEPs. The findings in this paper are important for engineers seeking to implement condition and health monitoring techniques on SiC power devices.

Electrothermal Effects on Hot Carrier Injection in n-Type SOI FinFET Under Circuit-Speed Bias

Electrothermal study of the n-type SOI Fin-FETs at 50-nm node is performed by analytical method and numerical algorithm. The self-heating effects (SHE) are investigated and validated by commercial software and other published analytical solutions. Further, the time-dependent thermal conduction equation is solved to get the temperature response under different signal stresses, including step pulse, AC signal, and circuit-speed random stress which is mimicked by the pseudorandom binary sequence (PRBS) signal. It is found that the PRBS signal leads to a lower transient temperature peak in the n-type FinFET of an inverter than the AC signal due to the less logic transitions in the PRBS, and signal with higher frequency induces worse SHE. According to the temperature response, hot-carrier injection (HCI)-induced threshold voltage shift (TVS) in the n-type FinFET of an inverter is further captured. It is shown that TVS under PRBS stress is much lower than that the AC case with the same frequency due to less logic transitions in PRBS signal, and the TVS becomes more severe with the increase of signal frequency. Although the gradual-width structure for n-type FinFET leads to a much lower static temperature, it does not help a lot to improve dynamic temperature and TVS when the inverter is biased by AC or PRBS signals.

The influence of lanthanum doping on the band alignment in Si/SiO2 /HfO2 gate stack of nano-MOSFETs: A first principles investigation

The induced threshold voltage shift due to La doping in HfO2 dielectric layer of n-type metal–oxide–semiconductor field effect transistors (MOSFETs) was studied using first principles calculations. Large supercells with state-of-the-art thicknesses for intermediate oxide (SiO2) and the high-k layer (HfO2) were employed. La2O3 complexes are shown to have the lowest formation energy at the SiO2/HfO2 interface. The induced shift in the band alignment depends on the position of La atoms in the dielectric stack and the desired shift for n-type transistors can be achieved with La doping at the SiO2/HfO2 interface.

Systematic Decomposition of the Positive Bias Stress Instability in Self-Aligned Coplanar InGaZnO Thin-Film Transistors

We propose an experimental method to decompose the positive gate-bias stress (PBS)-induced threshold voltage shift ( $\Delta {V}_{\mathsf {th}})$ of amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) into the contributions of distinct degradation mechanisms. Top-gate self-aligned coplanar structure TFTs are used for this letter. Stress-time-divided measurements, which combine the subgap density-of-states (DOS) extraction and the analysis on recovery characteristics, are performed to separate the $\Delta {V}_{\mathsf {th}}$ components. Change in excess oxygen ( $\text{O}_{\mathsf {ex}})$ -related DOS is clearly observed, and $\Delta {V}_{\mathsf {th}}$ by PBS is quantitatively decomposed into the contributions of the active $\text{O}_{\mathsf {ex}}$ , and the deep and shallow gate insulator traps. The quantitative decomposition of PBS-induced $\Delta {V}_{\mathsf {th}}$ provides physical insight and key guidelines for PBS stability optimization of a-IGZO TFTs.

P‐15: Prediction Method of Device Instability in a‐InGaZnO TFTs under Positive Gate Biases and Thermal Stresses using TCAD Simulation

The experimental and modeling study of bias and thermal stresses induced threshold voltage shift (ΔVTH) in amorphous indium‐gallium‐zinc oxide (a‐IGZO) thin film transistors (TFTs) has been investigated. The evolution of ΔVTH under positive biases and thermal stresses is dominated by charge trapping effect at channel and gate dielectric interface. We can predict the ƊVTH under different bias and thermal stresses using technology computer aided design (TCAD) device simulation if one measures once the device degradation at particular bias and temperature. Using this method, one can optimize the supply bias voltage and extend to predict the device lifetime.

Temperature-Dependent Gate Bias Stress Effect in Dioctylbenzothieno[2,3-b]benzothiophene-Based Thin-Film Transistor

We carried out a systematic research on temperature-dependent bias stress instability for Dioctylbenzothieno[2,3-b]benzothiophene-based organic thin-film transistors (OTFTs) below 200 K. 2-D grains boundaries model was employed to analyze the correlation between bias stress effects and the morphologies of first monolayer of the organic film. This enabled us to study the contribution to the shifts of threshold voltage from both grain boundaries and grains/dielectric interface by analyzing the temperature-dependent electrical properties. This paper may deepen our understanding of the bias stress induced threshold voltage shifts influenced by microstructures of the active layer and be helpful to the optimization the designation of poly-crystalline OTFTs.

Correlation of proton irradiation induced threshold voltage shifts to deep level traps in AlGaN/GaN heterostructures

The impact of proton irradiation on the threshold voltage (VT) of AlGaN/GaN heterostructures is systematically investigated to enhance the understanding of a primary component of the degradation of irradiated high electron mobility transistors. The value of VT was found to increase monotonically as a function of 1.8 MeV proton fluence in a sub-linear manner reaching 0.63 V at a fluence of 1 × 1014 cm−2. Silvaco Atlas simulations of VT shifts caused by GaN buffer traps using experimentally measured introduction rates, and energy levels closely match the experimental results. Different buffer designs lead to different VT dependences on proton irradiation, confirming that deep, acceptor-like defects in the GaN buffer are primarily responsible for the observed VT shifts. The proton irradiation induced VT shifts are found to depend on the barrier thickness in a linear fashion; thus, scaling the barrier thickness could be an effective way to reduce such degradation.

A Channel Stress-Profile-Based Compact Model for Threshold Voltage Prediction of Uniaxial Strained HKMG nMOS Transistors

In this paper, a physics-based compact model for the longitudinal and transverse stress profile in the channel of an uniaxially strained bulk MOS transistor is presented. The stress in the channel of a MOS transistor is not uniform and this nonuniform stress distribution results in higher average channel stress with reduction in the gate length. The developed model accurately predicts the average channel stress for different stress liners and transistor dimensions like gate length, gate height, and spacer width. The modeled average stress is then used to calculate the strain induced threshold voltage shift in HKMG nMOS transistors for different stress liners (fixed transistor dimensions) and for different transistor dimensions (fixed stress liner). The accuracy of the model is verified by comparing the threshold voltage shift with the experimental data obtained from the transistors fabricated in the 28 nm HKMG CMOS technology.

Grain Size and Interface Dependence of Bias Stress Stability of n-Type Organic Field Effect Transistors.

The effect of grain size and interface dependence of bias stress stability of C60-based n-type organic field effect transistors (OFETs) has been studied. It has been realized that, with increasing grain size of C60, the bias stress induced threshold voltage shift can be controlled and this effect is mainly attributed to the mechanism of charge trapping at grain boundaries. It is further studied that the growth of C60 on the surface of parylene at elevated substrate temperature leads to the creation of radicals at the interface between the active layer and the gate dielectric. These radicals help to improve the bias stress stability of C60-based n-type OFETs. For achieving the bias stress stability, we have presented a procedure of creation of radicals at the interface between C60 and parylene in single gate OFETs instead of dual gate OFETs.

Surface Roughness Influences on the ZnO Reram

The oxygen chemisorption raising from surface roughness associated with the formation/rupture of conductive filaments dramatically affects the electrical properties of ZnO ReRAM, which is confirmed by the oxygen adsorption induced threshold voltage shift of the FET measurements. The lower oxygen adatom concentration changes of rougher surface under various measuring ambient condition, leading to the improvement of the electrical property stability on both SET/RESET switching voltage and HRS/LRS resistance. The thickness-independent HRS resistance and the better switching probability shown in the ZnO with rougher surface, indicating that the oxygen chemisorption on the surface dominates resistive switching process. Our findings give a guidelines for developing practically useful applications of ZnO-based ReRAM.

The effect of gate overlap on the device degradation in IGZO thin film transistors

The effect of gate overlap on the device degradation in IGZO TFTs treated by H2 and Ar plasma was experimentally investigated after positive and negative gate biases stress and hot carrier stress. Using transmission line method, the effective channel length was extracted with the length of the gate overlaps. After positive and negative biases stress, the decrease of threshold voltage shifts with the increase of the gate overlaps may be attributed to the carrier diffusion from the n− extended source and drain regions to the intrinsic channel region. The hot carrier induced threshold voltage shifts were increased with the increase of the gate overlap due to the reduction of effective channel length.

Fourier spectrum based extraction of an equivalent trap state density in indium gallium zinc oxide transistors

Segregating the dynamics of gate bias induced threshold voltage shift, and in particular, charge trapping in thin film transistors (TFTs) based on time constants provides insight into the different mechanisms underlying TFTs instability. In this Letter we develop a representation of the time constants and model the magnitude of charge trapped in the form of an equivalent density of created trap states. This representation is extracted from the Fourier spectrum of the dynamics of charge trapping. Using amorphous In-Ga-Zn-O TFTs as an example, the charge trapping was modeled within an energy range of ΔEt≈ 0.3 eV and with a density of state distribution as Dt(Et−j)=Dt0exp(−ΔEt/kT)with Dt0 = 5.02 × 1011 cm−2 eV−1. Such a model is useful for developing simulation tools for circuit design.

Total ionizing dose effect in 0.2 μm PDSOI NMOSFETs with shallow trench isolation

This paper presents the total ionizing dose radiation performance of 0.2μm PDSOI NMOS devices under different bias conditions. The hump effect is observed in the transfer characteristic of the back gate device instead of the front gate device after radiation. A STI bottom corner parasitic transistor model is proposed to explain this phenomenon. It also provides a simple way to extract the effective sheet charge density along the STI sidewall. Three-dimensional simulation was applied to explain the radiation effect. It shows that charge trapped in the shallow trench isolation, particularly at the bottom region of the trench oxide where the STI and the BOX are connected, is the dominant contributor to the off-state drain-to-source leakage current. The dimension of the transistor plays an important role on influencing the device’s performance after radiation. Larger off-state leakage current and radiation induced threshold voltage shift are reported in the narrow channel device than in the wide channel one. Different TID responses due to the STI process variation are also discussed.

Zero interface dipole induced threshold voltage shift of HfO2/SiO2 gate dielectric stacks with NH3 plasma treatment

NH3 plasma treatment on interfacial SiO2 to reduce the interface dipole effect.Energy band diagram of HfO2 films established by XPS and UV-VIS.Band-gap increase due to tetragonal phase of nitrogen doped HfO2 examined by XRD.Negligible oxygen ions movement between HfO2/nitrided SiO2 for zero dipole interface. The NH3 plasma treatment on interfacial SiO2 has been proposed to reduce the interface dipole effect of HfO2/SiO2 gate dielectric stacks. The X-ray photoelectron spectroscopy (XPS) and ultraviolet-visible spectroscopy (UV-VIS) were used to establish the band diagram of the HfO2 films. The tetragonal crystallization phase of the HfO2 films examined by X-ray diffraction (XRD) was responsible for the band-gap increase during the NH3 plasma treatment. By using the Schottky emission and Fowler-Nordheim (F-N) tunneling, the effective electron barrier height of the Al/HfO2 gate stacks can be determined. Thus, the interface dipole and Fermi-level pinning induced flat-band voltage shifts of the Al/HfO2/SiO2/p-Si structure subjected to different NH3 plasma treatment conditions were obtained. It was found that the NH3 plasma treatment for about 4min was sufficient for achieving the zero dipole interface of the HfO2/SiO2 gate dielectric stack due to the negligible movement of the oxygen ions between the HfO2 and the nitrided oxide.