P‐15: Prediction Method of Device Instability in a‐InGaZnO TFTs under Positive Gate Biases and Thermal Stresses using TCAD Simulation

Abstract

The experimental and modeling study of bias and thermal stresses induced threshold voltage shift (ΔVTH) in amorphous indium‐gallium‐zinc oxide (a‐IGZO) thin film transistors (TFTs) has been investigated. The evolution of ΔVTH under positive biases and thermal stresses is dominated by charge trapping effect at channel and gate dielectric interface. We can predict the ƊVTH under different bias and thermal stresses using technology computer aided design (TCAD) device simulation if one measures once the device degradation at particular bias and temperature. Using this method, one can optimize the supply bias voltage and extend to predict the device lifetime.