Incremental Step Pulse Programming Research Articles

Novel strategies for low-voltage NAND flash memory with negative capacitance effect

Here, we present a novel approach to employing a negative capacitance (NC) phenomenon in the blocking oxide of charge trap flash (CTF) memory. To achieve this, we developed an inversible mono-domain like ferroelectric (IMFE) film through high-pressure post-deposition annealing in a forming gas at 200 atm (FG-HPPDA). The FG-HPPDA process enables to form a uniform alignment of domains and facilitates invertible domain switching behavior in ferroelectrics, generating an internal field by the flexo-electric effect as well as interface-pinned polarization by chemical reaction. Subsequently, to stabilize the NC effect, we fabricated the IMFE/Al2O3 heterostructure, which exhibits an outstanding capacitance-boosting feature. Finally, we successfully demonstrate unprecedented CTF memory with the NC effect in a blocking oxide. Our unique CTF device shows the improved performance (maximum incremental-step-pulse-programming (ISPP) slope ∼1.05) and a large MW (>8 V), attributed to the capacitance boosting by NC phenomenon.

Reliability Improvement in Vertical NAND Flash Cells Using Adaptive Incremental Step Pulse Programming (A-ISPP) and Incremental Step Pulse Erasing (ISPE)

Reliability Improvement in Vertical NAND Flash Cells Using Adaptive Incremental Step Pulse Programming (A-ISPP) and Incremental Step Pulse Erasing (ISPE)

Linear and symmetric synaptic weight update characteristics by controlling filament geometry in oxide/suboxide HfOx bilayer memristive device for neuromorphic computing

Memristive devices have been explored as electronic synaptic devices to mimic biological synapses for developing hardware-based neuromorphic computing systems. However, typical oxide memristive devices suffered from abrupt switching between high and low resistance states, which limits access to achieve various conductance states for analog synaptic devices. Here, we proposed an oxide/suboxide hafnium oxide bilayer memristive device by altering oxygen stoichiometry to demonstrate analog filamentary switching behavior. The bilayer device with Ti/HfO2/HfO2−x(oxygen-deficient)/Pt structure exhibited analog conductance states under a low voltage operation through controlling filament geometry as well as superior retention and endurance characteristics thanks to the robust nature of filament. A narrow cycle-to-cycle and device-to-device distribution were also demonstrated by the filament confinement in a limited region. The different concentrations of oxygen vacancies at each layer played a significant role in switching phenomena, as confirmed through X-ray photoelectron spectroscopy analysis. The analog weight update characteristics were found to strongly depend on the various conditions of voltage pulse parameters including its amplitude, width, and interval time. In particular, linear and symmetric weight updates for accurate learning and pattern recognition could be achieved by adopting incremental step pulse programming (ISPP) operation scheme which rendered a high-resolution dynamic range with linear and symmetry weight updates as a consequence of precisely controlled filament geometry. A two-layer perceptron neural network simulation with HfO2/HfO2−x synapses provided an 80% recognition accuracy for handwritten digits. The development of oxide/suboxide hafnium oxide memristive devices has the capacity to drive forward the development of efficient neuromorphic computing systems.

Investigation of Program Efficiency Overshoot in 3D Vertical Channel NAND Flash with Randomly Distributed Traps.

The incremental step pulse programming slope (ISPP) with random variation was investigated by measuring numerous three-dimensional (3D) NAND flash memory cells with a vertical nanowire channel. We stored multiple bits in a cell with the ISPP scheme and read each cell pulse by pulse. The excessive tunneling from the channel to the storage layer determines the program efficiency overshoot. Then, a broadening of the threshold voltage distribution was observed due to the abnormal program cells. To analyze the randomly varying abnormal program behavior itself, we distinguished between the read variation and over-programming in measurements. Using a 3D Monte-Carlo simulation, which is a probabilistic approach to solve randomness, we clarified the physical origins of over-programming that strongly influence the abnormal program cells in program step voltage, and randomly distributed the trap site in the nitride of a nanoscale 3D NAND string. These causes have concurrent effects, but we divided and analyzed them quantitatively. Our results reveal the origins of the variation and the overshoot in the ISPP, widening the threshold voltage distribution with traps randomly located at the nanoscale. The findings can enhance understanding of random over-programming and help mitigate the most problematic programming obstacles for multiple-bit techniques.

String-level compact modeling for dynamic operation and transient analysis of 3D charge trapping flash memory

In this article, we propose a string-level compact model, which is based on accurate and seamless channel electrostatic potential, for dynamic operation of 3D charge trapping flash (CTF) memory. First, we introduce a unit cell model for 3D CTF memory structure based on a conventional BSIM-CMG model using an extended netlist of equivalent circuits which describe the gate-all-around (GAA) structure composed of a metal gate, a blocking oxide, a charge trapping layer, and a tunneling oxide. Then, a string-level compact model is proposed, implying three advantages of inter-cell behaviors, seamless channel potential and process variation. To enhance the accuracy of the model behavior, extended model parameters are extracted showing good agreement with experimental data, such as I-V characteristics, program/erase speed, and incremental step pulse programming (ISPP). Furthermore, to predict channel electrostatic potential more precisely, we verify simulation program with integrated circuit emphasis (SPICE) simulation results of positively and negatively boosted channels comparing them with technology computer-aided design (TCAD) simulation results. Finally, we demonstrate that the proposed model can be efficiently applied to circuit simulation for analysis of the disturbance or failure mechanism and would equip the circuit designers and system architects with an effective tool for design optimization of 3D CTF memory devices.

Low-fluctuation nonlinear model using incremental step pulse programming with memristive devices

On-chip learning in neuromorphic systems, wherein both training and inference are performed on memristive synaptic devices, has been actively studied recently. However, on-chip learning is often affected by the weight-update linearity of memristive synaptic devices. Herein, we fabricated a Pt/Al2O3/TiOx/Ti/Pt stacked memristor device with excellent switching and reliability characteristics. Its weight-update linearity was analyzed via nonlinear A fitting through an on-chip simulation of the modified National Institute of Standards and Technology (MNIST) dataset. We confirmed the excellent recognition accuracy and low-fluctuation characteristics of the proposed model based on its similar characteristics to software learning. We obtained the perfect linear model and two types of nonlinear model characteristics of the memristor through incremental step pulse programming and performed an on-chip simulation. In addition, the characteristics of the measured cycle-to-cycle variation were reflected in the on-chip learning and were analyzed. We expect the low-fluctuation nonlinear model developed herein to be useful for on-chip learning owing to its excellent learning characteristics.

Fast and Accurate Weight Updating Strategy for Resistive Random-Access Memory (RRAM)-Based Neural Networks

The mathematical relationships between the operating voltages and the conductance of resistance random-access memory (RRAM) are found based on the statistical measurements of the 1-transistor 1-RRAM (1T1R) array. According to the corresponding relationships, a one-shot operation scheme without verification after programming is proposed for weight updating of RRAM-based neural networks. The proposed operation scheme enables parallel column-by-column SET and row-by-row RESET, which achieves fast and accurate conductance modulation in the 1T1R array. By utilizing the one-shot scheme for weight updating of the deep-Q network, the training efficiency improves 40 times compared with the incremental step pulse programming (ISPP) scheme.

Improved ISPP scheme for narrow threshold voltage distribution in 3-D NAND flash memory

Three-dimensional NAND flash technology exhibits a trend of increasing bit density. The narrow threshold voltage (Vth) distribution of each program state in a chip is important for increasing the number of bits in a multilevel cell (MLC) technique. An abnormal program cell (APC), which is an excessively programmed cell whose Vth overlaps with the next program state, increases the Vth distribution width (Wv). The wide Vth distribution makes it difficult to distinguish the data stored in each cell and causes data errors. In this study, an improved incremental step pulse programming (ISPP) method to narrow the Vth distribution has been proposed. As the programming step voltage (Vstep) decreases immediately before the target cells pass the nth program verify level (PVn), the difference between Vth and PVn decreases, causing a reduction in the number of APCs. Therefore, in the improved ISPP, the Vstep is selectively reduced at the target ISPP steps at which most cells are predicted to be programmed in the next ISPP step for each program state. As a result, the Wv of the improved scheme decreases compared to the conventional scheme with the minimum increase in the total number of program pulses. Larger bit density is feasible by applying improved ISPP, resulting in high-capacity NAND flash memory.

Dielectric-Engineered High-Speed, Low-Power, Highly Reliable Charge Trap Flash-Based Synaptic Device for Neuromorphic Computing beyond Inference.

The coming of the big-data era brought a need for power-efficient computing that cannot be realized in the Von Neumann architecture. Neuromorphic computing which is motivated by the human brain can greatly reduce power consumption through matrix multiplication, and a device that mimics a human synapse plays an important role. However, many synaptic devices suffer from limited linearity and symmetry without using incremental step pulse programming (ISPP). In this work, we demonstrated a charge-trap flash (CTF)-based synaptic transistor using trap-level engineered Al2O3/Ta2O5/Al2O3 gate stack for successful neuromorphic computing. This novel gate stack provided precise control of the conductance with more than 6 bits. We chose the appropriate bias for highly linear and symmetric modulation of conductance and realized it with very short (25 ns) identical pulses at low voltage, resulting in low power consumption and high reliability. Finally, we achieved high learning accuracy in the training of 60000 MNIST images.

Quantitative analysis of irregular channel shape effects on charge-trapping efficiency using massive 3D NAND data

The randomly fluctuating trap efficiency of taper-etched nanowire thin-film transistors was investigated by measuring a very large statistical ensemble of three-dimensional NAND flash memory cells. We made trapping in n-bit multi-level cells using incremental step pulse programming and observed the widening of the threshold voltage distribution caused by abnormal program cells. Further, we classified the components that broaden the threshold voltage distribution in both chip- and wafer-level measurements to analyze behaviors of the randomly fluctuating abnormal program cell. The variations in reading and programming operations are difficult to separate because they act simultaneously in the data reading and writing operations. For each pulse of the programming, the variations occur in reading for verification, in programming itself, and in reading after program completion. To analyze the inseparable variation, we used a method to extract only the intrinsic over-programming by removing variations in the read operation from the entire abnormal program cell. Using this extraction method, we could distinguish between the simultaneous read variation and over-programming. In particular, the unpredictable effect of the three-dimensional structure, such as the irregular shape and different radius due to the tapered channel hole profile from the nonideal etching process, was calculated and verified using experimental data. We quantitatively analyzed the experimental data one by one for each cell within the entire distribution, and each pulse of dozens in the programming scheme. This analysis provides quantitative information on the variations in charge-trapping efficiency and the threshold voltage distribution width by irregular-shaped tunneling layers.

Novel, parallel and differential synaptic architecture based on NAND flash memory for high-density and highly-reliable binary neural networks

A novel synaptic architecture based on a NAND flash memory structure is proposed as a high-density synapse capable of exclusive NOR (XNOR) operation for binary neural networks (BNNs). For the first time, a 4T2S-based synaptic architecture with a complementary input voltage that implements an equivalent bitwise XNOR operation is proposed. Two adjacent NAND flash strings connected with the word lines are used as one synaptic string with four input transistors connected to the bit-line. By changing the threshold voltage of the NAND flash cells and input voltages in a complementary fashion, the XNOR operation is successfully demonstrated. The large on/off current ratio (∼7 × 105) of the NAND flash cells and differential sensing scheme can implement high-density and highly reliable binary neural networks without error correcting codes (ECC), which can reduce the burden of the complementary metal–oxide–semiconductor (CMOS) overhead. Despite the string structure of NAND flash memory, the parallel read scheme significantly reduces the read-out latency when compared to the sequential read scheme. In addition, we show that with only 1 erase/program pulse, sufficiently low bit-error rate (7.6 × 10−9 %) is achieved without the conventional incremental step pulse programming (ISPP) scheme. Finally, the estimated synapse density of V-NAND flash memory with 128 stacks is ∼103 times that of the 2T2R synapse in resistive random access memory (RRAM).

TCAD simulation for capture/emission of carriers by traps in SiN: trap-assisted tunneling model extended for capture of carriers injected via Fowler–Nordheim tunneling

We propose the novel trap-assisted tunneling (TAT) model that incorporates the ability to calculate dissipation of the kinetic energy of carriers propagating in the conduction or valence band. The proposed model allows us to evaluate capture efficiency (or the capture cross section) of carriers injected into the SiN charge trap layer via Fowler–Nordheim tunneling. By applying our TAT model to large planar metal-oxide-nitride-oxide-semiconductor (MONOS) capacitors, experimental data showing that electron capture efficiency depends on the tunnel oxide thickness are physically interpreted. Furthermore, three-dimensional technology computer-aided design (TCAD) simulation using SiN trap parameters roughly extracted from planar MONOS data shows that the incremental step pulse programming characteristics calculated for the charge trap memory (CTM) prototype device are comparable with measured data. We have found that additional time to calculate SiN trap charges is less than only 5% of all remaining calculation time.

Quad-Level Cell Switching with Excellent Reliability in TiN/AlOx:Ti/TaOx/TiN Memory Device.

TiN/AlOx:Ti/TaOx/TiN memory devices using bilayer resistive switching memory demonstrated excellent durability and capability of QLC (quad-level cell) memory devices. The best nonvolatile memory characteristics with the lowest operation current and optimized 4 bit/cell states were obtained using the Incremental Step Pulse Programming (ISPP) algorithm in array. As a result, a superior QLC reliability (cycle endurance > 1 k at each level of the QLC, data retention > 2 h at 125 °C) for all the 4 bits/cell operations was achieved in sub-μm scaled RRAM (resistive random access memory) devices.

Cryogenic Operation of 3-D Flash Memory for Storage Performance Improvement and Bit Cost Scaling

This report introduces the cryogenic operation and storage performance of 3-D flash memory. The cell transistor characteristics and the basic functionalities, including read and program and erase (P/E) operations, are investigated at an extremely low temperature of 77 K cooled by the liquid nitrogen. The cell transistor has a steep subthreshold slope at 77 K compared with at 300 K, and the read operation is fully functional even though the saturation current becomes relatively small. P/E operations at 77 K are not much different from those at 300 K, and the same incremental-step pulse programming (ISPP) and incremental-step pulse erase (ISPE) methods are applicable. In addition, the storage performance and the reliability characteristics of 3-D flash memory, such as the read noise, the disturb characteristics, the data retention, and the cycle endurance, are also investigated. While there is no degradation in the disturb characteristics, the read noise at 77 K was significantly minimized compared with that at 300 K. The data retention characteristics are about three times improved, and the cycle endurance is about ten times improved at 77 K compared with at 300 K. These storage performance improvements and high-reliability characteristics at cryogenic operation enable us to achieve the ultramultilevel cell. We show the successful demonstration of 6-bit per cell (HLC) and discuss the impact of additional cooling cost and the possibility of future storage devices beyond HLC. The cryogenic operation of 3-D flash memory can greatly improve the storage performance and opens the door for potential new applications and the bit cost scaling for future storage devices.

A Noise-Resilient Neuromorphic Digit Classifier Based on NOR Flash Memories with Pulse–Width Modulation Scheme

In this work, we investigate the implementation of a neuromorphic digit classifier based on NOR Flash memory arrays as artificial synaptic arrays and exploiting a pulse-width modulation (PWM) scheme. Its performance is compared in presence of various noise sources against what achieved when a classical pulse-amplitude modulation (PAM) scheme is employed. First, by modeling the cell threshold voltage (VT) placement affected by program noise during a program-and-verify scheme based on incremental step pulse programming (ISPP), we show that the classifier truthfulness degradation due to the limited program accuracy achieved in the PWM case is considerably lower than that obtained with the PAM approach. Then, a similar analysis is carried out to investigate the classifier behavior after program in presence of cell VT instabilities due to random telegraph noise (RTN) and to temperature variations, leading again to results in favor of the PWM approach. In light of these results, the present work suggests a viable solution to overcome some of the more serious reliability issues of NOR Flash-based artificial neural networks, paving the way to the implementation of highly-reliable, noise-resilient neuromorphic systems.

Data Pattern Aware Reliability Enhancement Scheme for 3D Solid-State Drives

3D charge-trap (CT) NAND flash-based SSD has been used widely for its large capacity, low cost per bit, and high endurance. One-shot program (OSP) scheme, as a variation of incremental step pulse programming (ISPP) scheme, has been employed to program data for CT flash, whose program unit is the Word-Line (WL) instead of the page. The existing program optimization schemes either make trade-offs among program latency and reliability by adjusting the program step voltage on demand; or remap the most error-prone cell states to others by re-encoding programmed data. However, the data pattern, which represents the ratio of 1s in data values, has not been thoroughly studied. In this paper, we observe that most small files do not contain uniform 1s and 0s among these common file types (i.e., image, audio, text, executable file), leading to programming WL cells in different states unevenly. Some cell states dominate over the WL, while others are not. Based on this observation, we propose a flexible reliability enhancement scheme based on the OSP scheme. This scheme programs the cells into different states with varied , i.e., these cells in one state, whose number is the largest in one WL, are programmed with a fine-grained (namely slow write). In contrast, the minority are programmed with a coarse-grained (namely fast write). So the reliability is improved due to averaging the major enhanced cells with the minor degraded cells without program latency overhead. A series of experiments have been conducted, and the results indicate that the proposed scheme achieves 34% read performance improvement and 16% lifetime elongation on average.

The origin of oxide degradation during time interval between program/erase cycles in NAND Flash memory devices

This paper investigates the origin of NAND cell degradation during the time interval (t wait) between program/erase (P/E) cycles. It is observed that, at room temperature, the transconductance reduction is sensitive to from erase-to-program, and longer from erase-to-program results in larger In contrast, has almost no clear dependence on from program-to-erase. Using our previous statistical method, the activation energy () of oxide damage creation is extracted. As the starting voltage () of incremental step pulse programming (ISPP) varied from 14.6 to 17.6 V, has a shift of about 11 meV and 13 meV for both from erase-to-program of 0.1 s and 4 s, respectively. We also found that linearly decreases as the maximum oxide field increases during ISPP. It would be plausible to consider a model in which the program steps generated holes inside the tunneling oxide, which recombined with inversion electrons near Si/SiO2 interface during from erase-to-program. This process generates more trap states and thus results in larger

Program error mitigation in MLC NAND flash memory with soft decision decoders

Benefiting from strong decoding capabilities, soft-decision decoding has been used to replace hard-decision decoding in various communication systems, and NAND flash memory systems are no exception. However, soft-decision decoding relies heavily on accurate soft information. Owing to the incremental step pulse programming (ISPP), program errors (PEs) in multi-level cell (MLC) NAND flash memory have different characteristics compared to other types of errors, which is very difficult to obtain such accurate soft information. Therefore, the characteristics of the log-likelihood ratio (LLR) of PEs are investigated first in this paper. Accordingly, a PE-aware statistical method is proposed to determine the usage of PE mitigation schemes. In order to reduce the PE estimating workload of the controller, an adaptive blind clipping (ABC) scheme is proposed subsequently to approximate the PEs contaminated LLR with different decoding trials. Finally, simulation results demonstrate that (1) the proposed PE-aware statistical method is effective in practice, and (2) ABC scheme is able to provide satisfactory bit error rate (BER) and frame error rate (FER) performance in a penalty of negligible increasing of decoding latency.

Low Power Program Scheme With Capacitance-Less Charge Recycling for 3D NAND Flash Memory

This brief presents a capacitance-less charge recycling scheme to reduce the programming power of 3D NAND Flash memory. The charge recycling is accomplished with boost capacitors inside the wordline voltage generator itself, so that no extra capacitance is required. In order to implement this scheme, a proposed multifunctional charge pump and clock control method are introduced. Besides, the multifunctional charge pump also supports stage control, which can further reduce the power consumption. A wordline voltage generator with this proposed scheme has been fabricated in a 0.18 μm BCD process, and the effective chip area is 2.4mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Measurement results show that the total power consumption of Incremental Step Pulse Programming (ISPP) is reduced by 18.7% compared with the conventional one. What's more, the maximum peak current is reduced by 35%.

Origin of Incremental Step Pulse Programming (ISPP) slope degradation in charge trap nitride based multi-layer 3D NAND flash

We analyzed Incremental Step Pulse Programming (ISPP) slope degradation to improve the program efficiency of 3D NAND Flash memory using both measurement and simulation data. The simulation data are calibrated with the measurement data and they are in good agreement. The ISPP slope indicates program efficiency and its ideal value is 1. In reality, however, ISPP slope degradation (<1) occurs in the charge trap flash (CTF) memory and makes program speed slow. Two parameters affecting the ISPP slope degradation are quantitatively investigated: electron trap density (NT) and trap energy level (ET) of the charge trap nitride (CTN). There are optimal NT and ET fitted with 3D NAND Flash cell providing better program efficiency with lower retention loss. Detailed reasons are physically explained by observing the electron behaviors in various NT and ET values.