Abstract
In this work, we investigate the implementation of a neuromorphic digit classifier based on NOR Flash memory arrays as artificial synaptic arrays and exploiting a pulse-width modulation (PWM) scheme. Its performance is compared in presence of various noise sources against what achieved when a classical pulse-amplitude modulation (PAM) scheme is employed. First, by modeling the cell threshold voltage (VT) placement affected by program noise during a program-and-verify scheme based on incremental step pulse programming (ISPP), we show that the classifier truthfulness degradation due to the limited program accuracy achieved in the PWM case is considerably lower than that obtained with the PAM approach. Then, a similar analysis is carried out to investigate the classifier behavior after program in presence of cell VT instabilities due to random telegraph noise (RTN) and to temperature variations, leading again to results in favor of the PWM approach. In light of these results, the present work suggests a viable solution to overcome some of the more serious reliability issues of NOR Flash-based artificial neural networks, paving the way to the implementation of highly-reliable, noise-resilient neuromorphic systems.
Highlights
IntroductionDifferent memory solutions have been investigated for their adoption in neuromorphic systems and presented in literature
Artificial neural networks (ANNs) are computing systems that take inspiration from biological neural networks to address many problems involving unstructured data, such as image recognition and classification [1,2]
We have presented the implementation of a NOR Flash-based neuromorphic digit classifier based on pulse-width modulation (PWM)
Summary
Different memory solutions have been investigated for their adoption in neuromorphic systems and presented in literature They include works based on crossbar arrays of resistive elements, mainly resistive switching random access memories (RRAM) [3,4,5] and phase change memories (PCM) [6,7], or based on memory arrays of charge storage devices, such as NAND and NOR Flash memory arrays [8,9,10,11,12,13,14,15]. By means of a simulation-based analysis, we demonstrate, thanks to that PWM scheme, the possibility to achieve a tremendous reduction in classifier sensitivity to noise sources such as PN, RTN, and temperature variations The results of this analysis present a way to strongly relieve those issues, enabling the development of noise-resilient artificial neural networks based on scaled NOR Flash memory arrays.
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