Improvement In Power-delay Product Research Articles

Design of an area-efficient CMOS multiple-valued current comparator circuit

In the present state-of-the-art VLSI technology, the need for developing customised circuits to suit varying operating environments and specifications is escalating. The authors introduce an area-efficient current-mode comparator, which is based on modifications of the conventional CMOS current comparator. It has been verified by circuit simulations using the 0.25 /spl mu/m, 0.18 /spl mu/m, and 0.13 /spl mu/m CMOS technology from Chartered Semiconductor Manufacturing Pte. Ltd (CHRT ) that the proposed design acts as a perfect complement to the conventional current comparator for low threshold current (I/sub th/) levels. A low I/sub th/ is generally more favourable than a higher I/sub th/ as it tends to dissipate low static power. A more assuring and promising fact is that the area advantage becomes more significant with reducing feature size/technology. This attribute blends well with the contemporary and ongoing process technology miniaturisation. Together with the conventional and recently reported current comparator designs, the proposed current comparator has been integrated into a positive-digit adder (PDA) using the current-mode multiple-valued logic (CMMVL) approach with 1.8 V/0.18 /spl mu/m CMOS technology. The PDA utilising the new current comparator occupies a silicon area of only 40.2 /spl mu/m/sup 2/, which is only 77.2% and 22.6% of those of the conventional and contemporary circuits, with a power-delay product improvement of 7.3% and 70.4%, respectively.

Mosfet Scaling-the Driver of VLSI Technology

This is an introduction to the Classic Paper on MOSFET scaling by R. Dennard et al., Design of Ion-Implanted MOSFET's with Very Small Physical Dimensions,' published in the IEEE Journal of Solid-State Circuits in October 1974. The history of scaling and its application to very large scale integration (VLSI) MOSFET technology is traced from 1970 to 1998. The role of scaling in the profound improvements in power delay product over the last three decades is analyzed in basic terms.

High performance CMOS current comparator using resistive feedback network

A new high speed, low power and small area CMOS current comparator based on a resistive feedback network is proposed. Simulation results employing 0.35 /spl mu/m CMOS parameters demonstrate 7 ns response time and 0.45 mW power consumption for 0.1 /spl mu/A input current, which represents a /spl sim/400% improvement in power-delay product over existing current comparators. In this design, the bias current and the input impedance are well controlled parameters, and the inherent autozeroing scheme does not require any offset compensation.

Charge recycling differential logic (CRDL) for low power application

A novel logic family, called charge recycling differential logic (CRDL), has been proposed and analyzed. CRDL reduces power consumption by utilizing a charge recycling technique with the speed comparable to those of conventional dynamic logic circuits. It has an additional benefit of improved noise margin due to inherently static operation. The noise margin problem of true single-phase-clock latch (TSPC) is also eliminated when a CRDL logic circuit is connected to it. Two swing-suppressed-input latches (SSILs), which are introduced for use with CRDL, have better performance than the conventional transmission gate latch. Moreover, a pipeline configuration with CRDL in a true two-phase clocking scheme shows completely race-free operation with no constraints on logic composition. Eight-bit Manchester carry chains and full adders were fabricated using a 0.8 /spl mu/m single-poly double-metal n-well CMOS technology to verify the relative performance of the proposed logic family. The measurement results indicate that about 16-48% improvements in power-delay product are obtained compared with differential cascode voltage switch (DCVS) logic.

CMOS scaling for high performance and low power-the next ten years

A guideline for scaling of CMOS technology for logic applications such as microprocessors is presented covering the next ten years, assuming that the lithography and base process development driven by DRAM continues on the same three-year cycle as in the past. This paper emphasizes the importance of optimizing the choice of power-supply voltage. Two CMOS device and voltage scaling scenarios are described. One optimized for highest speed and the other trading off speed improvement for much lower power. It is shown that the low power scenario is quite close to the original constant electric-field scaling theory. CMOS technologies ranging from 0.25 /spl mu/m channel length at 2.5 V down to sub-0.1 /spl mu/m at 1 V are presented and power density is compared for the two scenarios. Scaling of the threshold voltage along with the power supply voltage will lead to a substantial rise in standby power compared to active power and some tradeoffs of performance and/or changes in design methods must be made. Key technology elements and their impact on scaling are discussed. It is shown that a speed improvement of about 7/spl times/ and over two orders of magnitude improvement in power-delay product (mW/MIPS) are expected by scaling of bulk CMOS down to the sub-0.1 /spl mu/m regime as compared with today's high performance 0.6 /spl mu/m devices at 5 V. However, the power density rises by a factor of 4/spl times/ for the high-speed scenario. The status of the silicon-on-insulator (SOI) approach to scaled CMOS is also reviewed, showing the potential for about 3/spl times/ savings in power compared to the bulk case at the same speed. >

Dependence of electron mobility on spatial separation of electrons and donors in AlxGa1−xAs/GaAs heterostructures

Single-period modulation doped A1xGa1−x As/GaAs heterojunctions have been prepared by molecular beam epitaxy (MBE). Heterojunctions with a Si-doped A1xGa1−x As layer grown on an unintentionally doped GaAs layer have exhibited enhanced mobility at 78 ° and 300 °K. The A1xGa1−x As, grown with x = 0.25 or x = 0.33, was doped to a level ND?3×1017 cm−3 resulting in a sheet-charge density of about 8×1011 cm−2. Maximum mobilities of 74 200 cm2/V s at 78 °K and 6930 cm2/V s at 300 °K were observed in different structures. This represents an improvement of more than a factor of 2 over the best previously reported results at 78 °K. These structures, if used for normally off and/or psuedonormally off FET channel layers in high-speed integrated circuits, can provide improved performance. These extremely high mobilities can lead to a power delay product improvement of about a factor of 2 at room temperature and a factor of more than 12 at liquid-nitrogen temperature as compared to conventional structures. This increase in mobility is the result of the virtual elimination of electron scattering by spacially separating the donors from the heterojunction interface.