Design of an area-efficient CMOS multiple-valued current comparator circuit

Abstract

In the present state-of-the-art VLSI technology, the need for developing customised circuits to suit varying operating environments and specifications is escalating. The authors introduce an area-efficient current-mode comparator, which is based on modifications of the conventional CMOS current comparator. It has been verified by circuit simulations using the 0.25 /spl mu/m, 0.18 /spl mu/m, and 0.13 /spl mu/m CMOS technology from Chartered Semiconductor Manufacturing Pte. Ltd (CHRT ) that the proposed design acts as a perfect complement to the conventional current comparator for low threshold current (I/sub th/) levels. A low I/sub th/ is generally more favourable than a higher I/sub th/ as it tends to dissipate low static power. A more assuring and promising fact is that the area advantage becomes more significant with reducing feature size/technology. This attribute blends well with the contemporary and ongoing process technology miniaturisation. Together with the conventional and recently reported current comparator designs, the proposed current comparator has been integrated into a positive-digit adder (PDA) using the current-mode multiple-valued logic (CMMVL) approach with 1.8 V/0.18 /spl mu/m CMOS technology. The PDA utilising the new current comparator occupies a silicon area of only 40.2 /spl mu/m/sup 2/, which is only 77.2% and 22.6% of those of the conventional and contemporary circuits, with a power-delay product improvement of 7.3% and 70.4%, respectively.