A Novel Mechanism for Delay-Insensitive Data Transfer Based on Current-Mode Multiple Valued Logic

Abstract

AbstractBy conventional delay-insensitive data encodings, the number of required wires for transferring N-bit data is 2N+1. To reduce the required number of wires to N+1, and thus, reducing complexity in designing a large scaled chip, a novel data transfer mechanism based on current-mode multiple valued logic is proposed. Effectiveness of proposed data transfer mechanism is validated by comparisons with conventional data transfer mechanisms using dual-rail and 1-of-4 encodings at the 0.25-μm CMOS technology. Simulation results of 32-bit data transfer with 10 mm wire length demonstrate that proposed data transfer mechanism reduces the time-power product values of dual-rail and 1-of-4 encoding by 55.5% and 8.5%, respectively, in addition to the reduction of the number of wire by about half.KeywordsReference CurrentCurrent MirrorWire LengthPower Supply NoiseWire ModelThese keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.