Cost-effective delay-insensitive data transfer mechanism using current-mode multiple valued logic

Abstract

In this paper, we propose a new data transfer mechanism based on delay-insensitive (DI) data coding with current-mode multiple valued logic (CMMVL). In previous DI data coding, the number of required wires for transferring N-bit data is 2N+1. However, only N+1 wires are needed in our transfer mechanism so it can contribute greatly to reducing the wire cost for designing a large scaled chip. We compare the proposed CMMVL circuit with conventional dual-rail DI encoding to validate its effectiveness through simulation in 0.25 /spl mu/m CMOS technology. In addition to advantage in wire cost, for 32 bit data transfer, simulation results show that the MVL version is superior to the dual-rail version by about 24.9% in the metric of time-power product. We also apply the MVL version to a practical environment such as an asynchronous bus architecture.