Improvement In Current Gain Research Articles

Improvements in current gain and breakdown voltage of silicon MIS heterojunction emitter transistors

Significant improvements in the current gain and in the breakdown voltage of high gain devices are reported for silicon-bipolar transistors. These improvements were obtained by the use of a heterojunction MIS tunneling emitter with the tunneling oxide properties more carefully optimized than in earlier devices. Common-emitter current gains above 3 × 104are reported for devices with a breakdown voltage above 30 V.

The influence of post-emitter processing on the current gain of bipolar transistors

The effects of post-emitter processing on the current gain of n-p-n and p-n-p transistors used in linear integrated circuits, is the subject of this paper. It is seen that during the emitter diffusion deep level impurities segregate into the bulk and space-charge regions of the emitter. The aluminum alloy process at 500°C provides a powerful scavenging action that getters the impurities. The post-alloy current gain increases by a factor of ten. This gettering is effective in phosphorus diffused emitters if the dielectric is either a CVD oxide, a plasma deposited oxide, or phosphorus glass under Si 3 N 4 . With thermally oxidized emitters there is no improvement in current gain. Boron diffused emitters, however, respond to the aluminum alloy process regardless of the dielectric. This study also identifies two processes that contribute to bandgap narrowing ( \DeltaE_{g} ) these are the emitter diffusion and the post-emitter thermal oxidation. A value of \DeltaE_{g} = 0.04 eV measured after the emitter diffusion was found to increase to 0.09 eV after thermal oxidation at 975°C. This additional component of \DeltaE_{g} is a result of the anomalous accumulation of phosphorus at the silicon surface during oxidation.

Current gain in bipolar transistors with a field plate over the base surface

Vertical n-p-n and lateral p-n-p transistor structures of an integrated circuit are studied using an electrolytic tank analogue and it is shown that the presence of a proper field plate extending from the collector-base junction over most of the base surface will improve the current-gain factor considerably. Experimental results of the analogue study, simulating typical carrier lifetimes and typical overall dimensions, are presented with various geometrical dimensions as parameters. Recently, a 2-dimensional electrolytic tank analogue 1 simu- lating volume recombination in the base region of bipolar transistors has been reported. The studies 1 ' 2 have shown that the current gain of transistors is limited by the excess stored charge in the transverse region of the base and also by the transverse diffusion of minority carriers into the base contact. This simulation study has also been adopted for the study of lateral p-n-p transistors 3 and it has been shown that the current gain of these transistors can be increased by providing a gap in the n + buried layer. The purpose of this paper is to study the effect of a field plate over the base surface and extending from the collector- base junction edge, on the current gain of vertical n-p-n transistors of integrated circuits, using an electrolytic tank analogue similar to the one discussed earlier. 1 3 It is shown that a field plate (i.e. m.o.s structure), spanning the major portion of the base surface (see Fig. la) and biased such that the region below is depleted, reduces the stored charge in the transverse region of vertical n-p-n transistors. The presence of this depletion region extending up to the collector-base junction, as shown in Fig. la, aids in improv- ing the collection of carriers injected in the transverse direction. Thus an improvement in current gain is achieved by reducing the recombination current and aiding the collection of carriers in the transverse region. In addition to the above, it is shown that a similar field-plate structure employed in lateral p-n-p transistors of integrated circuits would considerably improve their current gain. Sah 4 has given a detailed account of the effects of a field plate over the emitter-base junction of a vertical transistor and Grove 5 has discussed these results. Experimental measurements 6 on a specially designed, fabricated trans- istor with a field plate over the emitter-base junction for studying the surface effect on the current gain have shown that the base current and hence the current gain of the transistor depends upon the bias voltage on the metal electrode over the oxide protecting the emitter-base junc- tion. The present study of vertical n-p-n transistors is different from the above studies and the field plate extends from the collector-base junction over the major portion of the base surface. It may be noted that in the present study the field plate does not extend over the emitter-base junction (Fig. la) and hence the recombination effects discussed earlier 6 are not present in the proposed structure.

Inverse current gain improvement of bipolar transistors by double-base diffusion

The double-base diffusion process is introduced and is experimentally shown to significantly improve the inverse or upward current gain of the n-p-n bipolar transistor. The technique consists of a deep p <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> diffusion into an external base region of multicollector transistors forming a close-in collar around the intrinsic base of each transistor. This technique, together with the use of deep diffusion n <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> guard rings around the complete unit cell, is shown to improve the inverse current gain significantly.

A stability improvement of current gain in silicon planar transistors

Slow instability of current gain or the base current in silicon n-p-n planar transistors under large-current life tests in elevated temperatures is discussed. The instability is caused by the ion migration in the oxide bulk covering the intersection of emitter junction. Some results of experimental approach to make transistors insensitive to such a failure mode is also given.

Improvements in current gain and breakdown characteristics of silicon planar power transistors

Detailed experiments have been performed to determine the influence of various fabrication techniques, such as wafer preparation, diffusion profiles and transistor geometries on breakdown voltage (BVcBo) and current gain (β) characteristics of silicon planar n-p-n transistors. The geometries studied are circular, rectaugnlar and interdigital. The details of fabrication techniques which resulted in an increase of BVcBo and B from 12 volts to 30–50 volts and 12 to 30–70 respectively on 1 ohm-cm n-type collector material are reported.