Abstract
Detailed experiments have been performed to determine the influence of various fabrication techniques, such as wafer preparation, diffusion profiles and transistor geometries on breakdown voltage (BVcBo) and current gain (β) characteristics of silicon planar n-p-n transistors. The geometries studied are circular, rectaugnlar and interdigital. The details of fabrication techniques which resulted in an increase of BVcBo and B from 12 volts to 30–50 volts and 12 to 30–70 respectively on 1 ohm-cm n-type collector material are reported.
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