Speedup Improvement Research Articles

A parallelizable augmented Lagrangian method applied to large-scale non-convex-constrained optimization problems

We contribute improvements to a Lagrangian dual solution approach applied to large-scale optimization problems whose objective functions are convex, continuously differentiable and possibly nonlinear, while the non-relaxed constraint set is compact but not necessarily convex. Such problems arise, for example, in the split-variable deterministic reformulation of stochastic mixed-integer optimization problems. We adapt the augmented Lagrangian method framework to address the presence of nonconvexity in the non-relaxed constraint set and to enable efficient parallelization. The development of our approach is most naturally compared with the development of proximal bundle methods and especially with their use of serious step conditions. However, deviations from these developments allow for an improvement in efficiency with which parallelization can be utilized. Pivotal in our modification to the augmented Lagrangian method is an integration of the simplicial decomposition method and the nonlinear block Gauss–Seidel method. An adaptation of a serious step condition associated with proximal bundle methods allows for the approximation tolerance to be automatically adjusted. Under mild conditions optimal dual convergence is proven, and we report computational results on test instances from the stochastic optimization literature. We demonstrate improvement in parallel speedup over a baseline parallel approach.

Energy preserving model order reduction of the nonlinear Schrödinger equation

An energy preserving reduced order model is developed for two dimensional nonlinear Schrödinger equation (NLSE) with plane wave solutions and with an external potential. The NLSE is discretized in space by the symmetric interior penalty discontinuous Galerkin (SIPG) method. The resulting system of Hamiltonian ordinary differential equations are integrated in time by the energy preserving average vector field (AVF) method. The mass and energy preserving reduced order model (ROM) is constructed by proper orthogonal decomposition (POD) Galerkin projection. The nonlinearities are computed for the ROM efficiently by discrete empirical interpolation method (DEIM) and dynamic mode decomposition (DMD). Preservation of the semi-discrete energy and mass are shown for the full order model (FOM) and for the ROM which ensures the long term stability of the solutions. Numerical simulations illustrate the preservation of the energy and mass in the reduced order model for the two dimensional NLSE with and without the external potential. The POD-DMD makes a remarkable improvement in computational speed-up over the POD-DEIM. Both methods approximate accurately the FOM, whereas POD-DEIM is more accurate than the POD-DMD.

Fine-Grained Network Decomposition for Massively Parallel Electromagnetic Transient Simulation of Large Power Systems

Electromagnetic transient (EMT) simulation is one of the most complex power system studies that requires detailed modeling of the study system including all frequency-dependent and nonlinear effects. Large-scale EMT simulation is becoming commonplace due to the increasing growth and interconnection of power grids, and the need to study the impact of system events of the wide area network. To cope with enormous computational burden, the massively parallel architecture of the graphics processing unit (GPU) is exploited in this paper for large-scale EMT simulation. A fine-grained network decomposition, called shattering network decomposition, is proposed to divide the power system network exploiting its topological and physical characteristics into linear and nonlinear networks, which adapt to the unique features of the GPU-based massive thread computing system. Large-scale systems, up to 240 000 nodes, with typical components, including synchronous machines, transformers, transmission lines, and nonlinear elements, and multiple levels modular multilevel converter with up to 6144 submodules, are tested and compared with mainstream simulation software to verify the accuracy and demonstrate the speed-up improvement with respect to sequential computation.

A hybrid sample generation approach in speculative multithreading

Speculative multithreading (SpMT) is a thread-level automatic parallelization technique to accelerate sequential programs. Machine learning has been successfully brought into SpMT to improve its performance. An appropriate sample set, which plays the role of knowledge provider, is important for machine learning-based (ML-based) thread partition. Conventionally, heuristic rules-based (HR-based) sample generation approach cannot generate adaptive samples. A hybrid sample generation approach can break this bottleneck. With this method, we firstly automatically generate samples, which are MIPS codes consisting of spawning points (SPs) and control quasi-independent points (CQIPs) by heuristic rules; secondly manually adjust the positions of SPs and CQIPs and rebuild pre-computation slice to obtain better performance for every sample; and then build model to ensure that the probability of adjusting to the optimal partition positions is increasing. During the implementation of this approach, three measures: bias weighting, preservation of optimal solutions, summary of greedy rules, are taken. In this way, we enhance the adjustment frequency for subroutines with high called time and preserve the optimal partition positions, so to achieve a stable speedup improvement. On Prophet, which is a generic SpMT processor to evaluate the performance of multithreaded programs, SPEC2000 and Olden benchmarks are used as input. Experiments show that our approach can obtain better sample sets, which deliver a better performance improvement of about 86.9% on a 16 core than the samples generated by HR-based approach. Experiment results also prove that this approach is effective to generate sample sets for ML-based thread partition.

A parallel structure exploiting nonlinear programming algorithm for multiperiod dynamic optimization

This article develops a sequential quadratic programming (SQP) algorithm that utilizes a parallel interior-point method (IPM) for the QP subproblems. Our approach is able to efficiently decompose and solve large-scale multiperiod nonlinear programming (NLP) formulations with embedded dynamic model representations, through the use of an explicit Schur-complement decomposition within the IPM. The algorithm implementation makes use of a computing environment that uses the parallel distributed computing message passing interface (MPI) and specialized vector-matrix class representations, as implemented in the third-party software package, OOPS. The proposed approach is assessed, with a focus on computational speedup, using several benchmark examples involving applications of parameter estimation and design under uncertainty which utilize static and dynamic models. Results indicate significant improvements in the NLP solution speedup when moving from a serial full-space direct factorization approach, to a serial Schur-complement decomposition, to a parallelized Schur-complement decomposition for the primal-dual linear system solution within the IPM.

The home-forwarding mechanism to reduce the cache coherence overhead in next-generation CMPs

On the road to computer systems able to support the requirements of exascale applications, Chip Multi-Processors (CMPs) are equipped with an ever increasing number of cores interconnected through fast on-chip networks. To exploit such new architectures, the parallel software must be able to scale almost linearly with the number of cores available. To this end, the overhead introduced by the run-time system of parallel programming frameworks and by the architecture itself must be small enough in order to enable high scalability also for very fine-grained parallel programs. An approach to reduce this overhead is to use non-conventional architectural mechanisms revealing useful when certain concurrency patterns in the running application are statically or dynamically recognized. Following this idea, this paper proposes a run-time support able to reduce the effective latency of inter-thread cooperation primitives by lowering the contention on individual caches. To achieve this goal, the new home-forwarding hardware mechanism is proposed and used by our runtime in order to reduce the amount of cache-to-cache interactions generated by the cache coherence protocol. Our ideas have been emulated on the Tilera TILEPro64 CMP, showing a significant speedup improvement in some first benchmarks.

Distributed Algorithms for Improved Associative Multilabel Document Classification considering Reoccurrence of Features and handling Minority Classes

Existing work in the domain of distributed data mining mainly focuses on achieving the speedup and scaleup properties rather than improving performance measures of the classifier. Improvement in speedup and scaleup is obvious when distributed computing platform is used. But its computing power should also be used for improving performance measures of the classifier. This paper focuses on the same by considering reoccurrence of features and handling minority classes. Since it is very time consuming to run such complex algorithms on large datasets sequentially, distributed versions of the algorithms are designed and tested on the Hadoop cluster. Base associative classifier is designed based on multi-class, multi-label associative classification (MMAC) algorithm. Since no similar distributed algorithms exist, proposed algorithms are compared with the base classifier and have shown improvement in classifier performance measures.

Randomized LU decomposition using sparse projections

A fast algorithm that approximates a low rank LU decomposition is presented. In order to achieve a low complexity, the algorithm uses sparse random projections combined with FFT-based random projections. The asymptotic approximation error of the algorithm is analyzed and a theoretical error bound is presented. Finally, numerical examples illustrate that for a similar approximation error, the sparse LU algorithm is faster than recent state-of-the-art methods. The algorithm is completely parallelizable and can fully run on a GPU. The performance is tested on a GPU card showing a significant speed-up improvement in the running time in comparison to a sequential execution.

Yield and Speedup Improvements in Extensible Processors by Allocating Extra Cycles to Some Custom Instructions

In this article, we investigate the application of different techniques for mitigating the impact of process variations on the custom functional unit (CFU) of extensible processors. The techniques include using extra cycles for the CFU and extending the clock period for the extensible processor. The former technique is based on providing an extra clock cycle to those custom instructions (CIs) that have timing yields smaller than one. For this purpose, we make use of a lookup table (LUT) for each fabricated processor. Based on a post-fabrication analysis, the need for an extra clock cycle for some CIs is determined. Consequently, the CI timing violations are prevented, and all manufactured extensible processors will work with a predefined clock cycle time. To study the effect of the objective function (used during the CI selection phase) on the efficacy of the suggested architectural technique, we investigate three different objective functions. In the second technique, the clock period extension is used to guarantee a design yield of one. Our results demonstrate that combining both techniques helps increase the speedup achieved by the extensible processor. To assess the efficacies of the proposed methods, several benchmarks from different application domains are used. Results of the study reveal that the suggested techniques provide considerable improvements in the speedups of the extensible processors when compared to those of approaches that do not consider the impact of process variations.

GPU ACCELERATED DISCONTINUOUS GALERKIN TIME DOMAIN ALGORITHM FOR ELECTROMAGNETIC PROBLEMS OF ELECTRICALLY LARGE OBJECTS

In this paper, an efficient time domain simulation algorithm is proposed to analyze the electromagnetic scattering and radiation problems. The algorithm is based on discontinuous Galerkin time domain (DGTD) method and parallelization acceleration technique using the graphics processing units (GPU), which offers the capability for accelerating the computational electromagnetics analyses. The bottlenecks using the GPU DGTD acceleration for electromagnetic analyses are investigated, and potential strategies to alleviate the bottlenecks are proposed. We first discuss the efficient parallelization strategies handling the local-element differentiation, surface integrals, RK time-integration assembly on the GPU platforms, and then, we explore how to implement the DGTD method on the Compute Unified Device Architecture (CUDA). The accuracy and performance of the DGTD method are analyzed through illustrated benchmarks. We demonstrate that the DGTD method is better suitable for GPUs to achieve significant speedup improvement over modern multi-core CPUs.

Accelerating BWA Aligner Using Multistage Data Parallelization on Multicore and Manycore Architectures

Nowadays, rapid progress in next generation sequencing (NGS) technologies has drastically decreased the cost and time required to obtain genome sequences. A series of powerful computing accelerators, such as GPUs and Xeon Phi MIC, are becoming a common platform to reduce the computational cost of the most demanding processes when genomic data is analyzed. GPU has received more attention at literature so far. However, Xeon Phi constitutes a very attractive approach to improve performance because applications don’t need to be rewritten in a different programming language specifically oriented to it. Sequence alignment is a fundamental step in any variant analysis study and there are many tools that cope with this problem. We have selected BWA, one of the most popular sequence aligner, and studied different data management strategies to improve its execution time on hybrid systems made of multicore CPUs and Xeon Phi accelerators. Our main contributions are focused on designing new strategies that combine data splitting and index replication in order to achieve a better balance in the use of system memory and reduce latency penalties. Our experimental results show significant speed-up improvements when such strategies are executed in our hybrid platform, taking advantage of the combined computing power of a standard multicore CPU and a Xeon Phi accelerator.

OPLE

In this article, a heuristic custom instruction (CI) selection algorithm is presented. The proposed algorithm, which is called OPLE for “Optimization based on Partitioning and Local Exploration,” uses a combination of greedy and optimal optimization methods. It searches for the near-optimal solution by reducing the search space based on partitioning the identified CI set. The partitioning of the identified set guarantees the success of the algorithm independent of the size of the identified set. First, the algorithm finds the near-optimal CIs from the candidate CIs for each part. Next, the suggested CIs from different parts are combined to determine the final selected CI set. To improve the set of the selected CIs, the solution is evolved by calling the algorithm iteratively. The efficacy of the algorithm is assessed by comparing its performance to those of optimal and nonoptimal methods. A comparative study is performed for a number of benchmarks under different area budgets and I/O constraints. The results reveal higher speedups for the OPLE algorithm, especially for larger identified candidate sets and/or small area budgets compared to those of the nonoptimal solutions. Compared to the nonoptimal techniques, the proposed algorithm provides 30% higher speedup improvement on average. The maximum improvement is 117%. The results also demonstrate that in many cases OPLE is able to find the optimal solution.

A Reconfigurable Architecture for Binary Acceleration of Loops with Memory Accesses

This article presents a reconfigurable hardware/software architecture for binary acceleration of embedded applications. A Reconfigurable Processing Unit (RPU) is used as a coprocessor of the General Purpose Processor (GPP) to accelerate the execution of repetitive instruction sequences called Megablocks . A toolchain detects Megablocks from instruction traces and generates customized RPU implementations. The implementation of Megablocks with memory accesses uses a memory-sharing mechanism to support concurrent accesses to the entire address space of the GPP’s data memory. The scheduling of load/store operations and memory access handling have been optimized to minimize the latency introduced by memory accesses. The system is able to dynamically switch the execution between the GPP and the RPU when executing the original binaries of the input application. Our proof-of-concept prototype achieved geometric mean speedups of 1.60× and 1.18× for, respectively, a set of 37 benchmarks and a subset considering the 9 most complex benchmarks. With respect to a previous version of our approach, we achieved geometric mean speedup improvements from 1.22 to 1.53 for the 10 benchmarks previously used.

다시점 비디오 부호화를 위한 고속 계층적 탐색 기법

Motion estimation (ME) that limits the performance of image quality and encoding speed has been developed to reduce temporal redundancy in video sequences and plays an important role in digital video compression. But it is computational demanding part of the encoder. Multi-view video is obtained by capturing one three-dimensional scene with many cameras at different positions. ME for Multi-view video requires high computational complexity. To reduce computational complexity and maintain the image quality, a fast motion estimation method is proposed in this paper. The proposed method uses a hierarchical search strategy. This strategy method consists of modified diamond search patten, multi gird diamond search pattern, and raster search pattern. These search patterns place search points symmetrically and evenly that can cover the overall search area not to fall into the local minimum or exploits the characteristics of the distribution of motion vectors to place the search points. Experiment results show that the speedup improvement of the proposed method over TZ search method (JMVC) can be up to 1.2 ~3 times faster while maintaining similar video quality and bit rates.

Modified TZ Search Method for Motion Estimation in Multi-View Video Coding

Motion estimation (ME) plays an important role in digital video compression. But it requires huge complexity to find an optimal motion vector. Multi-view video is obtained by capturing one three-dimensional scene with many cameras at different positions. The computational complexity for motion estimation in multi view video coding increases in proportion to the number of cameras. To reduce computational complexity and maintain the image quality, a modified TZ search method for motion estimation in multi-view video coding is proposed in this paper. The proposed search method exploits the characteristics of the distribution of motion vectors to place the search points. Experiment results show that the speedup improvement of the proposed method over Pel Block Search and TZ search method (JMVC) can be up to more than 77 times and 1.8 ~4.5 times faster respectively by reducing the computational complexity and the image quality degradation is about to 0.05 ~ 1(dB) and 0.010.24 (dB) respectively.

다시점 비디오 부호화를 위한 저 복잡도 움직임 추정 탐색 기법

Although Motion estimation (ME) plays an important role in digital video compression, it requires a complicated search procedure to find an optimal motion vector. Multi-view video is obtained by capturing one three-dimensional scene with many cameras at different positions. The computational complexity of motion estimation for Multi-view video coding increases in proportion to the number of cameras. To reduce computational complexity and maintain the image quality, a low complexity motion estimation search method is proposed in this paper. The proposed search method consists of four-grid diamond search patten, two-gird diamond search pattern and TZ 2 Point search pattern. These search patterns exploit the characteristics of the distribution of motion vectors to place the search points. Experiment results show that the speedup improvement of the proposed method over TZ search method (JMVC) can be up to 1.8~4.5 times faster by reducing the computational complexity and the image quality degradation is about to 0.01~0.24 (dB).

Performance Evaluation of Parallel AES Implementations over CUDAGPU Framework

With a high computational complexity of encryption algorithm, AES, especially for huge real-time data, GPU has recently offered an alternate computational system instead of a traditional CPU (thread), incurring a significant improvement in speeding up the computational intensive parallel data encryption in various aspects - tremendous number of processing cores and non-generic computational processing architecture design. NVIDIA has developed a generic GPU programming platform and programming model, CUDA; however, a traditional AES CUDA implementation does not specify efficient techniques to utilize the GPU parallelism. As a result, in this research, we evaluate the recent proposed parallel AES implementations over GPU. In addition, to avoid the frequent shared memory access, we offer the possibility to rearrange AES stages to utilize the AES parallelism resulting in a momentous improvement of encryption speed-up over traditional GPU, and especially CPU.

Fast Pruned Interleaving

\boldmath In this paper, computationally efficient schemes for enumerating the so-called inliers of a wide range of permutations employed in pruned variable-size (turbo) interleavers are proposed. The objective is to accelerate pruned interleaving time in turbo codes by computing a statistic known as the pruning gap that enables determining a permuted address under pruning without serially permuting all its predecessors. It is shown that for any linear or quadratic permutation, including variations such as dithered relative prime or almost regular, the pruning gap can be computed in logarithmic time. Moreover, it is shown that Dedekind sums form efficient building blocks for enumerating inliers of the widely adopted polynomial-based permutations. An efficient algorithm for computing such sums in vector form using integer operations is presented. The results are extended to 2D and higher dimensional interleavers that combine multiple permutations along all dimensions, and closed-form expressions for inliers are derived. It is shown that the inliers statistic is a linear combination of the constituent permutation inliers. A lower bound on the minimum spread of serially pruned interleavers using the inliers statistic is also derived. Moreover, it is shown that serially pruned interleavers inherit the content-free property of the mother interleaver, and hence they are parallelizable. Simulation results of practical pruned turbo interleavers demonstrate a speedup improvement of several orders of magnitude compared to serial interleaving.

A fast approach to global alignment of protein-protein interaction networks.

BackgroundGlobal network alignment has been proposed as an effective tool for computing functional orthology. Commonly used global alignment techniques such as IsoRank rely on a two-step process: the first step is an iterative diffusion-based approach for assigning similarity scores to all possible node pairs (matchings); the second step applies a maximum-weight bipartite matching algorithm to this similarity score matrix to identify orthologous node pairs. While demonstrably successful in identifying orthologies beyond those based on sequences, this two-step process is computationally expensive. Recent work on computation of node-pair similarity matrices has demonstrated that the computational cost of the first step can be significantly reduced. The use of these accelerated methods renders the bipartite matching step as the dominant computational cost. This motivates a critical assessment of the tradeoffs of computational cost and solution quality (matching quality, topological matches, and biological significance) associated with the bipartite matching step. In this paper we utilize the state-of-the-art core diffusion-based step in IsoRank for similarity matrix computation, and couple it with two heuristic bipartite matching algorithms – a matrix-based greedy approach, and a tunable, adaptive, auction-based matching algorithm developed by us. We then compare our implementations against the performance and quality characteristics of the solution produced by the reference IsoRank binary, which also implements an optimal matching algorithm.ResultsUsing heuristic matching algorithms in the IsoRank pipeline exhibits dramatic speedup improvements; typically ×30 times faster for the total alignment process in most cases of interest. More surprisingly, these improvements in compute times are typically accompanied by better or comparable topological and biological quality for the network alignments generated. These measures are quantified by the number of conserved edges in the alignment graph, the percentage of enriched components, and the total number of covered Gene Ontology (GO) terms.ConclusionsWe have demonstrated significant reductions in global network alignment computation times by coupling heuristic bipartite matching methods with the similarity scoring step of the IsoRank procedure. Our heuristic matching techniques maintain comparable – if not better – quality in resulting alignments. A consequence of our work is that network-alignment based orthologies can be computed within minutes (as compared to hours) on typical protein interaction networks, enabling a more comprehensive tuning of alignment parameters for refined orthologies.

Combining recency of information with selective random and a victim cache in last-level caches

Memory latency has become an important performance bottleneck in current microprocessors. This problem aggravates as the number of cores sharing the same memory controller increases. To palliate this problem, a common solution is to implement cache hierarchies with large or huge Last-Level Cache (LLC) organizations. LLC memories are implemented with a high number of ways (e.g., 16) to reduce conflict misses. Typically, caches have implemented the LRU algorithm to exploit temporal locality, but its performance goes away from the optimal as the number of ways increases. In addition, the implementation of a strict LRU algorithm is costly in terms of area and power. This article focuses on a family of low-cost replacement strategies, whose implementation scales with the number of ways while maintaining the performance. The proposed strategies track the accessing order for just a few blocks, which cannot be replaced. The victim is randomly selected among those blocks exhibiting poor locality. Although, in general, the random policy helps improving the performance, in some applications the scheme fails with respect to the LRU policy leading to performance degradation. This drawback can be overcome by the addition of a small victim cache of the large LLC. Experimental results show that, using the best version of the family without victim cache, MPKI reduction falls in between 10% and 11% compared to a set of the most representative state-of-the-art algorithms, whereas the reduction grows up to 22% with respect to LRU. The proposal with victim cache achieves speedup improvements, on average, by 4% compared to LRU. In addition, it reduces dynamic energy, on average, up to 8%. Finally, compared to the studied algorithms, hardware complexity is largely reduced by the baseline algorithm of the family.