Improved Circuit Design Research Articles

HDLRuby: A Ruby Extension for Hardware Description and Its Translation to Synthesizable Verilog HDL

HDLRuby is a new hardware description language defined as an extension of the Ruby programming language aiming to improve circuit design productivity. HDLRuby allows to model digital circuits at the register transfer level while supporting high-level paradigms comprising object-oriented programming, genericity, metaprogramming, and reflection. By construction, HDLRuby can also execute any code in Ruby and supports all of its libraries. Yet, even if high-level features are beneficial for design productivity, such advantages can be negated if the design tools are not efficient enough for producing in reasonable time quality hardware. This article investigates this issue by presenting the techniques used for compiling HDLRuby descriptions and by evaluating their performance. In detail, it explains how the language has been implemented and how it is translated to synthesizable Verilog HDL. Experiments are then presented for confirming the productivity gain of using HDLRuby and for evaluating the performance of the translation, the size of the resulting code, and the time required by a commercially available synthesis tool to produce an FPGA configuration from it. The HDLRuby descriptions used for the experiments include a set of repetitive designs for single construct evaluations and the implementation of generic convolution neural networks for real-life applications. For these evaluations, the translation time proves to be more than 10 times shorter than the synthesis time.

Decoupled and modularized battery equalization circuit for equalization overlap issue

As the development of renewable energy sources, rechargeable batteries play a more and more important role in many applications such as energy storage systems and new energy vehicles. Numerous cells are usually combined to provide the desired energy and power capacity. Equalization circuits are therefore essential to eliminate the inconsistency of the cells. Most of the present equalization techniques neglect the critical issue of equalization overlap that some cells are charged and discharged repetitively in a single equalization process with redundant energy transfer. It induces the degeneration of the equalization performance and the health of the batteries. Even for some techniques without equalization overlap for the in-module equalization, this issue still appears when combining the modules into a pack due to the coupling relationship between the modules and the cells. To address this problem, this paper proposes a novel decoupled and modularized architecture of equalization circuit. With the improved circuit design and the dedicated algorithm, the equalization overlap can be eliminated as possible. Experimental results show that the proposed approach can obviously reduce the equalization loss and improve the equalization efficiency and speed in comparison with the conventional techniques.

Improved Circuit Design and Adaptive Burst Mode Control in PSFB Converters for Higher Efficiency Over a Wide Power Range

This paper presents an improved circuit design of Gallium Nitride (GaN) based phase shifted full bridge (PSFB) converters along with a new adaptive burst mode control strategy, to achieve high efficiency over a wide power range, including light loads. The main challenges of PSFB converters addressed in this paper are: load-dependent zero-voltage switching (ZVS), transformer saturation, and secondary side ringing. Since switching losses of GaN FETs are dominant at light loads, adaptive burst mode control can be employed to improve the efficiency at lower output power. By periodically switching output current between 0 A and minimum ZVS current, adaptive burst mode control can enable both smaller effective switching frequency and lower switching losses. A correction factor ‘k’ is adopted in the adaptive burst mode control’s current loop PI calculation so that the output current can switch fast without any overshoot that increases switches’ current stress. To verify the effectiveness of the proposed circuit and controller design, a 375 V input, 70 V output, 800 W PSIM simulation model as well as experimental prototype are developed and tested. The experimental results demonstrate the practical benefits of the proposed adaptive burst mode control.

Compound Control System of Hybrid Distribution Transformer

Hybrid distribution transformer (HDT) is a promising device for constructing the future active distribution network. To overcome the limitations of the existing HDT control schemes, a compound control scheme is proposed for an HDT with improved circuit design. In this design, the voltage source converter (VSC) for low-voltage side voltage regulation is moved to the medium-voltage side. The compound control scheme is developed based on the dynamic model of this new HDT, which explicitly considers the external disturbances. In this control scheme, two compound controllers are established to regulate the grid current and load voltage, respectively. For each compound controller, feedforward loops are integrated with the PI regulator, thus suppressing the disturbances. The key feature of this control scheme is that, by using the feedforward loops, the effect of external step disturbance can be equivalently weaken to an impulse disturbance and, hence, the system robustness can be improved. Simulation and experimental results validate the effectiveness of the proposed control scheme.

Improved Circuit Design of Analog Joint Source Channel Coding for Low-Power and Low-Complexity Wireless Sensors

To enable low-power and low-complexity wireless monitoring, an improved circuit design of Analog Joint Source Channel Coding (AJSCC) is proposed for wireless sensor nodes. This innovative design is based on Analog Divider Blocks (ADB) with tunable spacing between AJSCC levels. The ADB controls the switching between two types of Voltage Controlled Voltage Sources (VCVS). LTSpice simulations were performed to evaluate the performance of the circuit, and the power consumption and circuit complexity of this new ADB-based design were compared with our previous parallel-VCVS design. It is found that this improved circuit design based on ADB outperforms the design based on parallel VCVS for a large number of AJSCC levels (>= 16), both in terms of power consumption as well as circuit complexity, thus enabling persistent and higher temporal/spatial resolution environmental sensing.

RF and Microwave Hardware Challenges for Future Radio Spectrum Access

Radio technology for future broadband wireless applications presents a remarkable research opportunity for the RF transceiver and circuit design community. A survey is presented of the low-noise amplifier, frequency conversion, filtering, and transmitter techniques that are being explored for future wireless devices that require wide tuning range, flexible modulation formats, low dc power, and low cost. In all cases, the traditional disadvantages of broadband design approaches can be mitigated by taking advantage of higher levels of integration afforded by CMOS and BiCMOS technologies and improved circuit design approaches.

Optimization of SiGe bandgap-based circuits for up to 300 °C operation

An investigation of the performance and reliability issues associated with operating silicon–germanium (SiGe) devices and circuits at temperatures up to 300°C is presented, along with a new bypass compensation technique for optimizing bandgap reference performance at these extreme temperatures. In addition to the device-level characterization of a SiGe BiCMOS platform, improved circuit design and a device-level collector–substrate leakage suppression technique are shown to improve the viability of SiGe bandgap reference (BGR) circuits on low-cost, bulk Si wafers for high temperature applications. A shunting technique using various transistors to further improve BGR performance above 200°C is presented, and optimized compensation designs predict new performance records for a bulk-silicon based technology across temperatures from −200°C to 300°C. Finally, a closely-related SiGe temperature sensor circuit is characterized for operating environments up to 300°C.

Near-resonance electro-optic activity enhancement and improved modulation performance for polymer based Fabry–Pérot interferometers

Fabry–Pérot interferometers (FPIs) are designed to work near and off the absorption resonance of an electro-optic (EO) polymer. The near-resonance EO activity (EO coefficient r13∼25.4pm∕V at ∼1086nm) is enhanced over that off resonance (r13∼9.0pm∕V at ∼1526nm). The full width at half maximum of the FPI transmission band is ∼16nm near resonance compared to ∼22nm off resonance. The modulation performance can, therefore, be improved with a modulation ratio increased to ∼78% near resonance (at 1064nm) from ∼19% off resonance (at 1520nm). The modulation speed is approximately megahertz and can be increased to greater than gigahertz with improved circuit design.

HTS Sampler with Improved Circuit Design and Layout

This paper reviews our progress on the high-T c superconducting (HTS) sampler development, covering from the circuit design to the latest experimental data in the sinusoidal and pulse waveform measurements. A computer simulation has revealed that our sampler circuit with an improved design enables waveform measurement with the bandwidth over 100 GHz even with the thermal noise at around 40 K. Using the HTS sampler circuits fabricated employing an improved layout, we demonstrated waveform measurements for sinusoidal signals with frequencies of up to 50 GHz, the upper limit of the signal generator we used, both in the voltage-input-type system with a high-frequency input line and in the current-input-type one with a superconducting pickup coil. In the pulse measurement using an on-chip sampler, we succeeded in observing pico-second-order-wide single flux quantum (SFQ) current pulses, suggesting the potential bandwidth of our HTS sampler of more than 125 GHz.

Development of Computer Controlled FES System with Improved Circuit Design

Development of Computer Controlled FES System with Improved Circuit Design

Architectural and implementation challenges in designing high-performance RSFQ processors: A FLUX-1 microprocessor and beyond

This paper discusses the major challenges and solutions in designing high-performance superconductor processors in the context of the on-going collaboration between SUNY Stony Brook, TRW, and the JPL (NASA). It presents the architecture and organization of the first 8-bit FLUX-1 RSFQ microprocessor with a target clock frequency of 20 GHz fabricated in TRW's 4 kA/cm/sup 2/, 1.75-/spl mu/m Josephson junction technology in 2001-2002. A new parallel partitioned architecture has been developed for FLUX-1 in order to fill its long processing pipelines with operations, and reduce interconnect delays. The latest version of FLUX-1, called FLUX-1R, with improved circuit design characteristics and decreased power dissipation was fabricated in July 2002. FLUX-1R contains 63,107 Josephson junctions on a 10.35 mm /spl times/10.65 mm die with flip-chip packaging. The chip is currently under testing at TRW.

InGaAs/InP DHBT technology and design methodology for over 40 Gb/s optical communication circuits

High-performance technologies and adequate design methodologies are required to address the needs of very high-speed ICs (VHSICs) for over 40 Gb/s optical communications. We describe improvements we have introduced in our InP DHBT technology, and how our design methodology has evolved, we show how it results in improved circuit designs, and present some recent results, with some considerations on measurement limitations.

Interconnect scaling scenario using a chip level interconnect model

This paper describes an interconnect scaling scenario, which considers the impact of metal aspect ratio and pitch at each layer, new interconnect materials, and improved circuit design techniques. A new design methodology for a multilevel interconnect scheme is proposed on the basis of a chip level interconnect model. The design rule, the number of metal layers, and selection of interconnect materials at each device generation are projected using this methodology. It is shown that the 0.13-/spl mu/m CMOS generation requires not only new interconnect materials but also improved circuit design techniques such as variable pitch router and insertion of repeater buffers. A high-performance LSI in the 0.13-/spl mu/m CMOS generation needs seven layers using Cu interconnect and low-k dielectrics.

Scaling and Integration of High Performance Interconnects

ABSTRACTInterconnect delay is believed to have a dominating impact on the speed of large logic circuits (such as micro-processors) when the Si technology is scaled into sub- 0.25um generations. In this paper, we analyzed interconnect scaling issues based on leading micro-processor trend data, simple RC delay model and the “Rents' rule”. It was concluded that, in order to not limit the speed of large logic circuits, “fat” metal wires need to be used for upper metal layers, which will lead to a rapid increase of required number of metal layers (>10) for sub-0.25um technology generations. Introducing Cu and low ε interconnect system can delay this rapid increase by ∼1 generation. Creating multiple clock frequencies in large logic chips and reducing the size of high frequency islands appears effective in containing the interconnection delay problem. Therefore, the proposed interconnection scaling/development strategy is to introduce Cu and low ε dielectric into manufacturing in next 1∼3 generation (0.25um∼0.13um), develop low cost and high yield interconnect system to enable ∼10 interconnect layers, and improve circuit design methodology to reduce high frequency island size.

Improved Circuit Design of Multipeak Current–Voltage Characteristics Based on Resonant Tunneling Diodes

Improved multipeak circuits with two or three special resonant tunneling diodes (RTDs) connected in series are analyzed and discussed. There are four to seven peaks in the combined current–voltage ( I–V ) characteristics with three series-connected RTDs under different conditions. These phenomena occur only when these diodes satisfy certain constraint conditions between their electrical parameters. We will investigate and derive these constraint conditions. Using these constraint conditions, improved multipeak I–V characteristics can be obtained, and will greatly reduce circuit material in comparison with the traditional structure that stacks identical RTDs on top of each other. Also, equations are derived to simulate the combined I–V characteristics to compensate the lack of RTD model in the SPICE program.

Exit switch for radiotherapy treatment rooms

An improved circuit design for a radiotherapy treatment room exit alarm and interlock is described and compared with simpler circuits. The unique self test and fail safe features are discussed. All component values are given for the unit which has been in successful operation for over one year.

Improved circuit design for electrostatic self-resonating vibroscopes

In this paper a new circuit design for automatic electrostatic vibroscopes is presented. Previously, the component which stabilized the self-oscillatory motion of the filament in the feedback loop of electrostatic vibroscopes was a negative temperature coefficient thermistor. In the present system this device is replaced with a programmable analog compander. This modification represents an improvement because response time is faster, the steady-state conditions are more stable, and the overall performance of the vibroscope is less susceptible to errors caused by changes in environmental conditions.

High Speed 1k-bit Static RAM Using DSA MOST's

A high speed, fully static, 1024 word × 1 bit random access memory has been developed, using improved Diffusion Self-Aligned (DSA) MOS transistors, reduced design rule (3µm) and an improved circuit design. The RAM is TTL compatible and operates with a single power supply of 5V without an internal bias generator. Address access time is 10 ns and power dissipation is 480mW at a standard power supply of 5V.

A Digitally Controlled Color Television Camera

Today's trend toward extensive on-the-spot live color broadcasting of news and sports events has pointed up the need for a highly mobile studio-performance color camera. Approximately two and a half years ago a system design was formulated with prime consideration given to the requirement for a compact, rugged, lightweight camera that would be highly mobile and still maintain the high performance and operational features of the studio-type camera. Its small size and light weight were made possible by improved circuit design and new state-of-the-art components and construction techniques. The following items were of particular importance in reducing the size and weight of the system: a 1-in broadcast quality Plumbicon pickup tube; a small-size, lightweight lens with elements of higher light transmission; specialized integrated and thick-film hybrid circuits; computer-type digital control circuits; high-density multi-layer printed circuit cards; and multiplexing techniques enabling the use of triaxial cable