Improvement Of Carrier Lifetime Research Articles

Minority carrier lifetime and efficiency improvement of multicrystalline silicon solar cells by two-step process

Impurities and defects are of significant interest in multicrystalline silicon, due to the detrimental effect they can have on carrier lifetimes and electrical properties. In view of that, it is important to incorporate certain processing steps to decrease the recombination activities. In this study, a novel experiment was applied as a beneficial approach to improve the electronic quality of low-resistivity mc-Si substrates via a two-step process. Initially, the first step involves gettering multicrystalline substrates using sacrificial porous silicon layer on both sides, which was introduced as a simple sequence for efficient extrinsic gettering schemes. The gettering experiment was performed at 600–900 °C, and optimum results were obtained at 900 °C. Then, the second step involves coating the front surface of gettered mc-Si at 900 °C with vanadium oxide that serves as an excellent antireflection layer and leads to improve furthermore the electrical properties. Significant improvements were obtained after the deposition of vanadium oxide antireflection coating, in view of the fact that gettered mc-Si substrate at 900 °C provides the highest minority carrier lifetime and the lowest effective surface recombination velocity. An overall increase of the electrical properties was obtained after the described two-step process. The conversion efficiency increases from 6% (reference) and reached 13.7%.

Defect properties of Sb- and Bi-doped CuInSe2: The effect of the deep lone-pair s states

Bi or Sb doping has been used to make better material properties of polycrystalline Cu2(In,Ga)Se2 as solar cell absorbers, including the experimentally observed improved electrical properties. However, the mechanism is still not clear. Using first-principles method, we investigate the stability and electronic structure of Bi- and Sb-related defects in CuInSe2 and study their effects on the doping efficiency. Contrary to previous thinking that Bi or Sb substituted on the anion site, we find that under anion-rich conditions, the impurities can substitute on cation sites and are isovalent to In because of the formation of the impurity lone pair s states. When the impurities substitute for Cu, the defects act as shallow double donors and help remove the deep InCu level, thus resulting in the improved carrier life time. On the other hand, under anion-poor conditions, impurities at the Se site create amphoteric deep levels that are detrimental to the device performance.

Enhancement in solar hydrogen generation efficiency using InGaN photoelectrode after surface roughening treatment with nano-sized Ni mask

A significant enhancement in solar hydrogen generation efficiency has been achieved by inductive coupled etching (ICP) surface roughening treatment using nano-sized nickel mask. As much as 7 times improvement of photocurrent is demonstrated in comparison with a planar one fabricated from the same parent wafer. Under identical illumination conditions in HBr solution, the incident photon conversion efficiency (IPCE) shows an enhancement with a factor of 3, which even exceed 54% at 400 nm wavelength. We believe the enhancement is attributed to several facts including improvement in absorption, reacting area, carrier localization and carrier lifetime.

Annealing of Electron Irradiated, Thick, Ultrapure 4H SiC between 1100°C and 1500°C and Measurements of Lifetime and Photoluminescence

Ultra-pure n-type (8×1013 cm-3), 99 μm thick epitaxial films of 4H SiC were electron irradiated at 170 keV with a fluence of 5×1016 cm-2 or at 1 MeV with a fluence of 1×1015 cm-2 in various geometries. Low temperature photoluminescence (LTPL) spectra and microwave photoconductance (μPCD) lifetime measurements were obtained on all samples prior to annealing and after annealing in Argon in free standing mode or on a POCO carbon platform, every 50°C from 1100°C to 1500°C. No improvement in carrier lifetime was obtained. Spurious lines attributable to the use of a Genesis CX 3550Å laser are also reported.

High sheet resistance emitter c-Si solar cells with low SRV by local line contact with transparent conducting oxides

The high sheet resistance (Rs) solar cells with ITO full contact suffer from low open circuit voltage (Voc) with a negligible/no passivation effect. To overcome this, we approached ITO local line contact with SiO2 passivation to reduce the recombination loss. Passivation area increases to 91.29%. The improvement in carrier lifetime, Voc, reveals the melioration in passivation. With high Rs emitter, the ITO full contact solar cell results in efficiency of 16.26% whereas the ITO local line contact solar cell results in 17.15%.

Surface depletion and electrical transport model of AlInP-passivated GaAs nanowires

Fabrication, current–voltage characterization and analytical modeling of an AlInP-passivated GaAs nanowire (NW) ensemble device are presented. During fabrication, sonication was used as a novel and crucial step to ensure effective contacting of the NWs. Current–voltage characteristics of the passivated NW devices were fitted using an analytical surface depletion and transport model which improves upon established models by implementing a non-uniform density of GaAs surface states and including a NW diameter distribution. Scanning electron microscopy, capacitance–voltage characterization and secondary ion mass spectrometry were used to fix key parameters in the model. A 55% decrease in surface state density was achieved upon passivation, corresponding to an impressive four order of magnitude increase in the effective carrier concentration of the NWs. Moreover, the thickest NWs in the ensemble were found to dictate the device characteristics, which is a behavior that should be common to all ensemble NW devices with a distribution in radius. As final confirmation of effective passivation, time-resolved photoluminescence measurements showed a 25× improvement in carrier lifetime upon passivation. The fabrication and passivation methods can be easily implemented into future optoelectronic applications.

Point defect reduction and carrier lifetime improvement of Si- and C-face 4H-SiC epilayers

The impact of two post-growth processes, namely, C+-implantation/annealing process and thermal oxidation/annealing process, on trap concentrations in thick n-type 4H-SiC epilayers was studied for both Si- and C-face. Conditions such as the implantation dose and annealing temperature of the C+-implantation/annealing processes were optimized for Si-face epilayers, and consequently the Z1/2 center was eliminated up to 100 μm or more, and the minority carrier lifetime reached 13 μs while maintaining a good surface morphology. The effect of the process conditions on the creation of new traps, including ON1 center, was also studied in both Si- and C-face epilayers. The ON1 center was introduced in both Si- and C-face by two post-growth processes, although the concentration was found to vary according to the polar face and the post-growth processes. The mechanism of the different impacts on Z1/2 center reduction and ON1 center creation by the two post-growth processes on Si- and C-face is discussed.

Demonstration of Lateral IGBTs in 4H-SiC

Lateral insulated gate bipolar transistors (IGBTs) in 4H-SiC are demonstrated for the first time. The devices were fabricated based on three different designs to investigate the effects of buffer doping and carrier lifetime on device performance. Experimental results show that, with a lightly doped buffer, a short drift region length, and an improved carrier lifetime, the common base current gain of the parasitic bipolar junction transistor (BJT) is improved, leading to a higher current capability of the IGBT. The differential on-resistance of the lateral IGBT with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Ld</i> = 20 μm is smaller than that of a lateral MOSFET counterpart, implying partial conductivity modulation in the drift region.

Comparison of Post-Growth Carrier Lifetime Improvement Methods for 4H-SiC Epilayers

We compare two methods for post-growth improvement of bulk carrier lifetime in 4H-SiC: dry oxidations and implantations with either 12C or 14N, followed by high temperature anneals in Ar atmosphere. Application of these techniques to samples cut from the same wafer/epilayer yields 2- to 11-fold lifetime increases, with the implantation/annealing technique shown to give greater maximum lifetimes. The maximum lifetimes reached are ~5μs after 12C implantation at 600°C and annealing in Ar for 180 minutes at 1500°C. Higher temperatures give decreased lifetimes, a result which differs from reports in literature.

The Effects of Offset Spacer on nMOSFET Hot-Carrier Lifetime

In this paper, the effects of offset spacer on nMOSFET hot-carrier lifetime have been investigated. In this process, the offset spacer consists of silicon oxide formed by CVD in traditional poly/SiON gate process after poly etch and re-oxidation, which is found to reduce the gate-to-drain overlap capacitance (Cgd0) as well as the short channel effect (SCE). Intuitively, the reduction of Cgd0 will worsen the hot carrier performance. However, it is found that, the device with offset spacer has about four times hot carrier lifetime improvement in IO nMOSFET, compared to the case without offset spacer. Much decreased substrate current is seen in the process with offset spacer. Technology Computer-Aided Design (TCAD) simulation results show that with the application of offset spacer, much longer hot carrier lifetime is achieved, contributed by the reduced Emax and optimized Emax location, even though the Cgd0 is reduced.

Sensitization of nickel oxide: improved carrier lifetime and charge collection by tuning nanoscale crystallinity

A new record conversion efficiency of 0.61% that stands for a 50% increase in current dye-sensitized NiO photocathode in iodide-triiodide electrolyte was achieved by simply tuning the nanoscale crystallinity of NiO.

Development of Low RON,Diff, 12 kV, 4H-SiC GTOs For High-Power and High-Temperature Applications

In this paper, we report our recently developed 1 × 1 cm2, 12 kV SiC GTOs with a very low differential on-resistance (RON,Diff) of 4 mΩ·cm2 with respect to the device active area at high injection level current of 100 A/cm2 or higher, which is more than a 40% reduction from our previously reported work. This significant reduction in the on-resistance was attributed to an improvement of carrier lifetime in the SiC bulk region. The SiC GTO was wire-bonded and attached to a high-voltage package before the high-temperature measurement. Forward characteristics of the device were then measured using a Tektronics 371 curve tracer from room temperature up to 400°C. Over the temperature range, the RON,Diff of the 4H-SiC GTO increased modestly from 4 mΩ·cm2 at 20°C to 4.7 mΩ·cm2 at 400°C, while the forward voltage drop at 100 A decreased slightly from 3.97 V at 20°C to 3.6 V at 400°C. The gate to cathode blocking voltage (VGK) was measured using a customized high-voltage test set-up. The leakage current was measured 0.66 μA at a VGK of 12 kV at 20°C.

Reduced auger recombination in mid-infrared semiconductor lasers

A quantum-design approach to reduce the Auger losses in λ = 2 μm InGaSb type-I quantum well edge-emitting lasers is reported. Experimentally realized structures show a ∼3 × reduction in the threshold, which results in 4.6 × lower Auger current loss at room temperature. This is equivalent to a carrier lifetime improvement of 5.7 × and represents about a 19-fold reduction in the equivalent “Auger coefficient.”

Dislocation structure of GaN films grown on planar and nano-patterned sapphire

Plane view and cross-section transmission electron microscopy (TEM) images were used to compare the density, character, and curvature of dislocations developed during metalorganic vapor phase epitaxy (MOVPE) of GaN on planar c-plane sapphire with those developed during growth on nano-patterned c-plane sapphire. Scanning electron microscopy (SEM) characterization of GaN films at different stages of growth for both types of substrates complemented the TEM investigation. GaN growth on wafers patterned with an array of submicron sapphire bumps exhibited relatively uniform nucleation and initial growth, as well as early island coalescence. It is suggested that this coalescence results in a relatively small fraction of dislocations with partial screw character at the surface of the films grown on the patterned substrate, and that this may be responsible for the improvements in carrier lifetime and device efficiency seen in earlier studies on similar sapphire substrates.

Understanding of Passivation Mechanism in Heterojunction c-Si Solar Cells

ABSTRACTIntrinsic hydrogenated amorphous silicon (a-Si:H) films can yield in outstanding electronic surface passivation of crystalline silicon (c-Si) wafers as utilized in the HIT (heterojunction with intrinsic thin layer) solar cells. We have studied the correlation between the passivation quality and the interface nature between thin amorphous layers and an underlying c-Si substrate for understanding the passivation mechanism. We found that a thin (∼5nm) intrinsic layer is inhomogeneous along the growth direction with the presence of a hydrogen rich layer at the interface and that completely amorphous films result in better passivation quality and device performance than an epitaxial layer. Post annealing improves carrier lifetime for the amorphous layer, whereas the annealing is detrimental for the epitaxial layer. We have also found that the passivation quality of intrinsic a Si:H(i) film deteriorates severely by the presence of a boron-doped a-Si:H(p+) overlayer due to Si-H rupture in the a-Si:H(i) film. Finally, for a passivation layer in the hetero-junction structure, a-Si1−xOx will be demonstrated in comparison with a-Si:H.

Reduction of Traps and Improvement of Carrier Lifetime in SiC Epilayer by Ion Implantation

Reduction in deep level defects and increase of carrier lifetime in 4H-SiC epilayer was observed after carbon ion implantation into the shallow surface layer of 250 nm and subsequent annealing above 1400 °C. The concentration of Z1/2 and EH6/7 traps was determined by deep level transient spectroscopy 4 μm below the implanted layer. After annealing, concentration of both traps decreased from 1013 cm-3 range to below the detection limit. Minority carrier lifetime almost doubled in the implanted samples compared to the unimplanted samples. We suggest that carbon interstitials from the implanted layer in-diffuse into the layer underneath during annealing and annihilate with carbon vacancies. Our results indicate that Z1/2 and EH6/7 traps are most likely carbon vacancy related.

Reduction of traps and improvement of carrier lifetime in 4H-SiC epilayers by ion implantation

The authors report a significant reduction in deep level defects and improvement of carrier lifetime in 4H-SiC material after carrying out carbon or silicon ion implantation into the shallow surface layer of 250nm and subsequent annealing at 1600°C or higher temperature. Reduction of Z1∕2 and EH6∕7 traps from 3×1013cm−3 to below the detection limit (5×1011cm−3) was observed by deep level transient spectroscopy in the material 4μm underneath the implanted layer. Minority carrier lifetime almost doubled in the implanted samples compared to the unimplanted samples. The authors propose that the implanted layer acts as a source of carbon interstitials which indiffuse during annealing and accelerate annealing out of grown-in defects in the layer underneath the implanted region.

Effects of rapid thermal annealing on optical quality of GaNP alloys

Significant improvements in radiative efficiency of GaNP epilayers grown on GaP substrates by solid-source molecular beam epitaxy (MBE) are achieved by post-growth rapid thermal annealing (RTA). From temperature-dependent CW and time-resolved photoluminescence (PL) spectroscopies combined with PL excitation measurements, the observed improvements are attributed to annealing out of competing nonradiative centres. This conclusion is supported by the following experimental evidence: reduced thermal quenching of the PL intensity resulting in a substantial (up to 18 times) increase at room temperature (RT) after RTA, and simultaneous improvements in carrier lifetime at RT deduced from time-resolved PL measurements.

Photocurrent spectroscopy of solution-grown CdS films annealed in CdCl2 vapour

Thin cadmium sulfide (CdS) films (100–130 nm) are deposited on glass from an alkaline solution. The films are annealed in air, in the vicinity of a CdCl2 source, at different temperatures (280–400°C) and for different time periods (below 75 min). The change in some of the optoelectronic parameters (resistivity, direct and indirect transition energies) as a result of annealing is studied using modulated photocurrent spectroscopy. The experimental results reveal that annealing in air, in the absence of a CdCl2 source, reduces the bandgap energy of CdS by 0.12 eV due to the formation of valence-band states. Annealing in CdCl2 vapour removes the tail states and establishes the bulk bandgap (2.42 eV). It also increases the film's photoconductivity by a factor of 10 under white light illumination of intensity 100 mW cm−2, yielding a dark-to-light resistivity ratio of 3 × 104. The film's optoelectronic properties are controlled by two defect energy levels that are located at 0.14 and 1.30 eV below the conduction band edge. The increase in photoconductivity by annealing is due to the improvement of excess carrier lifetime as a result of changes in the 1.30 eV energy level.

Characterization of polycrystalline Si silicon sheet grown by die casting combined with the Bridgman technique

ABSTRACTDie-casting growth was used for manufacturing the multicrystalline silicon sheet with a size of 100 × 120 × 0.5 mm. During the growth, incorporation of contaminants such as iron, cobalt, nickel and chromium was well suppressed. The average etch-pit density values ranged from 1×104 cm-2 to 4x106 cm-2 for growth rates of 5 to 60 mm/h, respectively. Measurement of minority-carrier lifetime bye microwave-photoconductivity-decay (μ-PCD) method was 0.5 μs for as-grown specimens, suggesting that defects and residual strain exist in the grown sheet. Moreover, post heat treatment at 1473 K reduced the etch-pit density and improved carrier lifetime up to 2.2 μs.