The Effects of Offset Spacer on nMOSFET Hot-Carrier Lifetime

Abstract

In this paper, the effects of offset spacer on nMOSFET hot-carrier lifetime have been investigated. In this process, the offset spacer consists of silicon oxide formed by CVD in traditional poly/SiON gate process after poly etch and re-oxidation, which is found to reduce the gate-to-drain overlap capacitance (Cgd0) as well as the short channel effect (SCE). Intuitively, the reduction of Cgd0 will worsen the hot carrier performance. However, it is found that, the device with offset spacer has about four times hot carrier lifetime improvement in IO nMOSFET, compared to the case without offset spacer. Much decreased substrate current is seen in the process with offset spacer. Technology Computer-Aided Design (TCAD) simulation results show that with the application of offset spacer, much longer hot carrier lifetime is achieved, contributed by the reduced Emax and optimized Emax location, even though the Cgd0 is reduced.