Design and analysis of improved logic halo LDD NMOSFETs robust to HCI stress, using TCAD numerical models

Abstract

An improved low-voltage logic halo-type lightly-doped drain (LDD) NMOSFET robust to hot-carrier injection (HCI) stress is proposed. The well-designed NMOSFET meets all device design specifications of the hot-carrier injection reliability lifetime, the threshold voltage, the drain saturation current, the off-state current, the substrate current and the off-state breakdown voltage. Technology computer-aided design (TCAD) process and device simulations were essentially used for design and analysis of the robust device and for providing device design curves and physical insights. Key TCAD models and methods for simulating the hot-carrier injection-induced degradation are the kinetic equations for MOSFET HCI degradation, the spherical harmonics expansion (SHE) method, and the hydrodynamic model. TCAD model parameters were calibrated against experimental data to improve accuracy of static and transient simulations. Simulation results show that the hot-carrier injection degradation depends strongly on the LDD implant condition and halo/pocket channel engineering. The centered halo located between the source and the drain LDD of the improved NMOSFET controls short-channel effects effectively, while maintaining targeted hot-carrier reliability lifetime. The HCI reliability lifetime of the well-designed centered-halo phosphorus LDD NMOSFET is 3.1 times longer than a conventional halo phosphorus LDD NMOSFET. They all meet the lifetime specification longer than 0.2 years.