Impedance Transformation Network Research Articles

A compact lumped‐element two‐way differential to single‐ended Wilkinson power combiner with embedded impedance transformation

AbstractThis letter presents a compact lumped‐element two‐way differential to single‐ended Wilkinson power combiner with embedded impedance transformation. It consists of two transformer baluns and two parallel resistance and capacitor (RC) branches. The two transformers generate high‐order impedance transformation networks at even‐mode operation and form resonators together with the two parallel RC branches at odd‐mode operation, thus achieving broadband impedance matching and power combining with a compact area. A proof‐of‐concept prototype working at 1.7 GHz is designed and fabricated. Measurement results show that the peak isolation is 24.5 dB, insertion loss is from 0.34 to 1.15 dB and magnitude and phase imbalance are within 0.1 dB and , respectively, over the frequency range from 1.37 to 1.97 GHz. The area is only 6.54 mm 6 mm.

Novel Design Space of Broadband High-Efficiency Parallel-Circuit Class-EF Power Amplifiers

This article proposes a broadband high-efficiency parallel-circuit (PC) class-EF power amplifier (PA) along with a quarter-wavelength stub for the first time. By adding a reactive element <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${X}$ </tex-math></inline-formula> , the design space is expanded so that the impedance terminations of the fundamental and harmonics are no longer fixed points. Based on the broadband capability of the proposed structure, using a GaN HEMT transistor, a proof-of-concept circuit implemented with the Chebyshev impedance transformation network is designed and fabricated. Experimental results demonstrate a high-efficiency broadband PA operating from 2.6-3.9 GHz, with the average efficiency of 71.5%, the measured output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${P}_{\textit {out}}$ </tex-math></inline-formula> ) of 38.8-40.9 dBm and the power gain of 8.5-10.6 dB.

A W-Band SPDT Switch With 15-dBm P1dB in 55-nm Bulk CMOS

Power-handling capability of bulk CMOS-based single-pole double-throw (SPDT) switch operating in millimeter-wave (mm-wave) and subterahertz region is significantly limited by the reduced threshold voltage of deeply scaled transistors. A unique design technique based on impedance transformation network (ITN) is presented in this work, which improves 1-dB compression point, namely P1dB, without deteriorating other performance. To prove the presented solution is valid, a 70–100-GHz switch is designed and implemented in a 55-nm bulk CMOS technology. At 90 GHz, it achieves a measured P1dB of 15 dBm, an insertion loss (IL) of 3.5 dB, and an isolation (ISO) of 18 dB. The total area of the chip is only 0.14 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

A 220‐GHz CMOS passive subharmonic downconverter for low‐IF applications

This paper presents a 220-GHz subharmonic downconverter with high conversion gain (CG) and low noise figure (NF) implemented in 28 nm bulk CMOS, including a core mixer and an intermediate frequency (IF) amplifier. Based on the traditional quasi-subharmonic mixer, new gate-shorted technology is presented to improve NF and CG by adding a source inductor to reduce the loss of radiofrequency signals. In addition, the impedance transformation network provides passive voltage gain to suppress the noise of the IF amplifier. The downconverter achieves a minimum single-sidebandNF of 15.5 dB and a maximum CG of 21.3 dB when the IF frequency is 10 MHz. The 1 dB compression point of the downconverter is −30 dBm and consumes 8 mA current with an operating voltage of 0.9 V. The core area of the chip is 200 × 160 µm2

A 9 dB back‐off dual‐band asymmetric Doherty power amplifier using dual peaking amplifiers for reactance compensation

AbstractThis paper proposes a dual‐band asymmetric Doherty power amplifier (ADPA) with 9 dB power back‐off range using dual parallel peaking amplifiers to realize reactance compensation for wideband operation at two frequency bands. To achieve dual‐band amplification, the specific phase delays of the carrier and peaking output matching networks (OMNs) required on the two target frequency bands were determined using the phase delay period repeatability principle combined with the Doherty impedance transformation first. Then, the carrier and peaking OMNs were designed according to the desired phase delay. More specifically, two parallel peaking amplifiers using the low‐order impedance transformation network were combined to generate the desired compensating reactance at the back‐off power range for wideband operation. For verification, a dual‐band ADPA operating over 2.35–2.75 and 3.2–3.6 GHz frequency bands was designed and measured. Experimental results show that, for the two frequency bands, the efficiencies at saturation are 53.6%–64.3% and 48%–67.8%, with the 9 dB back‐off efficiencies reaching 41.5%–53.3% and 40.5%–52.8%, respectively. When stimulated by a 20 MHz modulated signal, the designed ADPA can achieve the adjacent channel leakage ratio of −48 dBc after linearization.

A 24–44 GHz Broadband Transmit–Receive Front End in 0.13-μm SiGe BiCMOS for Multistandard 5G Applications

In this article, a novel broadband millimeter-wave (mm-wave) front end (FE) based on the asymmetric switch network structure is proposed for multistandard fifth-generation (5G) applications. The asymmetric switch network consists of a bidirectional impedance transformation network and a T-type topology single-pole single-throw (SPST) switch. In the TX-mode, the bidirectional impedance transformation network serves as an output matching network to achieve a continuous-mode Class-F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-1</sup> power amplifier (PA) to expand the bandwidth. In the RX-mode, the OFF impedance of the PA can be transformed into a high-impedance region by the bidirectional impedance transformation network. Based on the proposed structure, a broadband mm-wave front end is implemented in the 0.13- μm SiGe BiCMOS process, which occupies 906 μm ×997 μm including pads. In the TX-mode, the -1-dB P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> bandwidth of the FE covers 21-44 GHz with the maximum output power of 18.1-19 dBm and the peak power added efficiency (PAE) of 20.2%-26.8%. In the RX-mode, the FE achieves an 84.6% and -3-dB small-signal gain fractional bandwidth from 20.2 to 49.8 GHz with 38-mW power consumption. It achieves a measured noise figure (NF) of 7.62-11.64 dB over the frequency range of 24-48 GHz. To the best of our knowledge, this is the first FE that covers all the present 5G mm-wave bands without reconfiguration.

A 2–20-GHz 10-W High-Efficiency GaN Power Amplifier Using Reactive Matching Technique

In this article, we present the analysis, design, and implementation of a wideband 10-W monolithic microwave integrated circuit power amplifier (PA), fabricated in a low-cost 0.1-μm gallium nitride (GaN) on Si technology. The design is focused on the realization of a low-loss and wideband impedance transformation networks across 2-20 GHz using a reactive matching (RM) technique. The two-stage GaN PA achieves an average output power of 40.1 dBm and a peak output power of 41.6 dBm at 13 GHz, in the CW-mode operation, with a smallsignal gain of S <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">21</sub> > 25.5 dB over the entire bandwidth. The average power-added efficiency (PAE) is 21%, with a peak PAE of 29% at 6 GHz. The PA chip occupies an area of 2.9×2.6 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To the best of our knowledge, the PA presented in this work demonstrates the highest broadband gain among the reported GaN-based RMPAs with a corresponding output power of about 10 W.

Bandwidth Improvement of MMIC Single-Pole-Double-Throw Passive HEMT Switches with Radial Stubs in Impedance-Transformation Networks

In this paper, we propose a new configuration for improving the isolation bandwidth of MMIC single-pole-double-throw (SPDT) passive high-electron-mobility transistor (HEMT) switches operating at millimeter frequency range. While the conventional configuration adopted open-stub loading for compensation of the off-state capacitance, radial stubs were introduced in our approach to improve the operational bandwidth of the SPDT switch. Implemented in 0.15 m GaAs pHEMT technology, the proposed configuration exhibited a measured insertion loss of less than 2.5 dB with better than 30 dB isolation level over the frequency range from 33 GHz to 44 GHz. In terms of the bandwidth of operation, the proposed configuration achieved a fractional bandwidth of 28.5% compared to that of 12.3% for the conventional approach. Such superior bandwidth performance is mainly attributed to the less frequency dependent nature of the radial stubs.

Planar Dual-Band Branch-Line Coupler With Large Frequency Ratio

This work presents a novel planar branch-line coupler topology developed for dual-band operation using an E-shaped impedance transformer network to supplant the conventional microstrip line. Explicit closed-form design equations for dual-band operation are derived using the ABCD matrices. The studied coupler features a large dual-band frequency ratio with a compact size. A prototype coupler centered at 1 and 8 GHz is first presented and experimentally examined to demonstrate the large frequency ratio. Further, another prototype coupler centered at 2.4 and 5.2 GHz for potential WLAN applications is also developed and experimentally characterized. Measurements and simulations for both prototype couplers show good performance within the studied dual-band frequencies.

Design and Analysis of a Continuously Tunable Low Noise Amplifier for Software Defined Radio.

This paper presents the design and analysis of a continuously tunable low noise amplifier (LNA) with an operating frequency from 2.2 GHz to 2.8 GHz. Continuous tuning is achieved through a radio frequency impedance transformer network in the input matching stage. The proposed circuit consists of four stages, namely transformer stage, tuning stage, phase shifter and gain stage. Frequency tuning is controlled by varying output current through bias voltage of tuning stage. The circuit includes an active phase shifter in the feedback path of amplifier to shift the phase of the amplified signal. Phase shift is required to further achieve tunability through transformer. The LNA achieves a maximum simulated gain of 18 dB. The LNA attains a perfect impedance match across the tuning range with stable operation. In addition, it achieves a minimum noise figure of 1.4 dB.

A Near-Zero-Power Wake-Up Receiver Achieving −69-dBm Sensitivity

This paper presents the design of a wake-up receiver (WuRX) that both improves sensitivity and reduces power over prior art through a multi-faceted design featuring an off-chip impedance transformation network with large passive voltage gain, an active envelope detector with high input impedance to facilitate large passive voltage gain, a low-power precision comparator, and a low-leakage digital baseband correlator. Implemented in a 180-nm silicon on insulator CMOS process using dynamic threshold-voltage MOSFET (DTMOS) devices, the OOK-modulated WuRX operates at 113.5 MHz and achieves a sensitivity of −69 dBm, while consuming just 4.5 nW from a 0.4-V supply.

Globally Optimal Matching Networks With Lossy Passives and Efficiency Bounds

Impedance transformation is one of the central concepts in high-frequency circuits and systems and is used ubiquitously for optimal power matching, noise matching, and high-efficiency power delivery to the antenna by power amplifiers. The matching network can be generally expressed as a path on the Smith chart and given the load and source impedances, there are theoretically infinite ways to achieve the transformation. When losses are included, each path will encounter a different loss, and currently, no comprehensive theory exist for finding the most optimal matching network. Furthermore, the networks will also provide different bandwidths of operation. Due to the matching network losses, it is often not optimal to force conjugate matching for maximizing end-to-end power transfer efficiency. In this paper, we provide a method toward finding 1) the globally most efficient path between two arbitrary impedances with lossy passives; 2) given the source and the load impedances, the optimal (typically non-conjugate) impedance to match and the highest efficiency path to reach the impedance; and 3) upper bounds on achievable efficiencies under the various scenarios. This paper also proposes ways to combine this method with nonlinear load-pull simulations for optimal combiner and matching network for integrated power amplifiers. This analysis creates interesting ways to maximize efficiency and bandwidths simultaneously and the paper also discusses this joint optimization. To the best of our knowledge, this is the first comprehensive analysis of globally optimal impedance transformation networks between arbitrary impedances with lossy passives.

Efficiency Optimized Distributed Transformers for Broadband Monolithic Millimeter-Wave Integrated Power Amplifier Circuits

This paper revises the efficiency optimization equations for magnetic-transformer-based power combiner/ divider impedance transformation networks (e.g., distributed active transformer). It evaluates their usability for high millimeter-wave frequencies, where the distributed behavior of a transformer and its loss become relevant. As is demonstrated, the standard optimization equations do not lead to an optimum result. To enable the optimization of distributed transformers, an extended lumped equivalent circuit model is proposed and used for the derivation of new optimization equations. The novel equations enable the design of magnetic transformers with maximum efficiency. To demonstrate the performance that can be achieved with optimized distributed magnetic transformer networks at millimeter-wave frequencies, measurement results of an R-band (i.e., 170–260 GHz)/H-band (i.e., 220–325 GHz) power amplifier (PA) are presented. With an output power of approximately 6.2 dBm at 260 GHz, the amplifier is among the state of the art for mHEMT PAs operating in this frequency range. With its relative 3-dB bandwidth of 29%, however, it surpasses all those reported mHEMT PAs to date.

Design of 6–18-GHz High-Power Amplifier in GaAs pHEMT Technology

This paper presents a design procedure for a wideband 6–18-GHz monolithic microwave integrated circuit high-power amplifier (HPA) in 0.25- $\mu \text{m}$ AlGaAs-InGaAs pHEMT technology. The design is mainly focused on the realization of the passive circuits to provide the required low-loss and wideband impedance transformation networks. The two-stage GaAs HPA achieves an average output power of 39.6 dBm and a peak output power of 40.5 dBm at 11 GHz, in pulsed mode operation, with a small-signal gain of $S_{21}>10$ dB over the entire bandwidth. The average power added efficiency (PAE) is 22%, with a peak PAE of 29% at 11 GHz. The HPA chip occupies an area of $5\times 3.6~\mathrm {mm}^{2}$ . The achieved output power and the corresponding power density of 0.51 W/ $\mathrm {mm}^{2}$ are amongst the highest reported values in wideband GaAs HPAs.

A Novel Design Methodology for High-Efficiency Current-Mode and Voltage-Mode Class-E Power Amplifiers in Wireless Power Transfer systems

The high-efficiency current-mode (CM) and voltage-mode (VM) Class-E power amplifiers (PAs) for MHz wireless power transfer (WPT) systems are first proposed in this paper and the design methodology for them is presented. The CM/VM Class-E PA is able to deliver the increasing/decreasing power with the increasing load and the efficiency maintains high even when the load varies in a wide range. The high efficiency and certain operation mode are realized by introducing an impedance transformation network with fixed components. The efficiency, output power, circuit tolerance, and robustness are all taken into consideration in the design procedure, which makes the CM and the VM Class-E PAs especially practical and efficient to real WPT systems. 6.78-MHz WPT systems with the CM and the VM Class-E PAs are fabricated and compared to that with the classical Class-E PA. The measurement results show that the output power is proportional to the load for the CM Class-E PA and is inversely proportional to the load for the VM Class-E PA. The efficiency for them maintains high, over 83%, when the load of PA varies from 10 to 100 $\Omega$ , while the efficiency of the classical Class-E is about 60% in the worst case. The experiment results validate the feasibility of the proposed design methodology and show that the CM and the VM Class-E PAs present superior performance in WPT systems compared to the traditional Class-E PA.

A 70–80-GHz SiGe Amplifier With Peak Output Power of 27.3 dBm

This paper presents a fully integrated 16-way power-combining amplifier for 67–92-GHz applications in an advanced 90-nm silicon germanium HBT technology. The 16-way amplifier is implemented using three-stage common-emitter single-ended power amplifiers (PAs) as building blocks, and reactive $\lambda $ /4 impedance transformation networks are used for power combining. The three-stage single PA breakout has a small-signal gain of 22 dB at 74 GHz, and saturation output power ( $P_{\mathrm{ sat}}$ ) of 14.3–16.4 dBm at 68–99 GHz. The power-combining PA achieves a small-signal gain of 19.3 dB at 74 GHz, and $P_{\mathrm{ sat}}$ of 25.3–27.3 dBm at 68–88 GHz with a maximum power added efficiency of 12.4%. The 16-way amplifier occupies 6.48 mm2 (including pads) and consumes a maximum current of 2.1 A from a 1.8 V supply. To the best of our knowledge, this is the highest power silicon-based $E$ -band amplifier to date.

A SiGe Multiplier Array With Output Power of 5–8 dBm at 200–230 GHz

This paper presents an integrated four-way power-combining multiplier for 200–230-GHz applications in an advanced 90-nm silicon germanium HBT technology. The active multiplier is implemented using balanced transistor pairs driven by pseudodifferential power amplifiers (PAs) at 100–120 GHz and the outputs at 200–240 GHz are power combined using reactive $\lambda $ /4 impedance transformation networks. A single multiplier breakout results in an output power of 1.8 dBm at 245 GHz with a peak conversion gain of −15.5 dB. The power-combining multiplier achieves an output power of 8 dBm at 215 GHz and >5 dBm at 200–230 GHz. A peak conversion gain of 1.6 dB is achieved at an output power of $\sim 0$ dBm at 215 GHz. The four-way combined multiplier occupies 3.63 mm2, including pads, and consumes 1.2 A from a 1.8 V supply mainly due to the differential 100–120-GHz PAs. To the best of our knowledge, this is the highest output power achieved in multipliers and amplifiers among all silicon-based technology to-date at frequencies above 200 GHz and with a record wide bandwidth.

Design of a Post-Matching Asymmetric Doherty Power Amplifier for Broadband Applications

In this letter, the design of a broadband asymmetric Doherty power amplifier (ADPA) with an 800 MHz (41% fractional) bandwidth is presented. The post-matching structure and low-order impedance transformation networks (ITN) are employed to achieve the broadband performance. Meanwhile, different drain biases on the main and peaking devices are used to run the asymmetric operation. The proposed ADPA shows high-efficiency performance at 8–9 dB output power back-off (OBO) throughout the whole 800 MHz band. The ADPA has been designed and implemented using commercial GaN HEMTs to validate the OBO and broadband characteristics. Maximum output power ranges from 43.7 to 45.2 dBm, 50.4%-56.2% efficiencies at 8–9 dB OBO are measured from 1.55 to 2.35 GHz.

A Three-Way Reconfigurable Power Divider/Combiner

In this paper, a three-way reconfigurable power divider/combiner is proposed based on novel switch element with matching network (SEMN) and reconfigurable impedance transformer network (RITN). A good matching performance and a high isolation of the SEMN with one p-i-n diode can be obtained by the parasitic inductance and reverse capacitance of the p-i-n diode involved in matching circuits. With different parameters of one p-i-n diode under forward bias and reverse bias, the reconfigurable impedance matching can be obtained by the RITN with a simple structure. By using four RITNs and nine SEMNs, the three-way reconfigurable power divider/combiner can provide seven different states in the three-path mode, the two-path mode, and the single-path mode. For verification, a 5-GHz three-way reconfigurable power divider/combiner is designed and fabricated. In the three-path mode, measured insertion losses from port 1 to transmission ports (port 2, port 3, and port 4) are less than 0.74 dB and the isolations between transmission ports are higher than 32.1 dB. In the two-path mode with three states, the measured insertion losses are less than 0.93 dB; the isolations between transmission ports, transmission ports and isolation ports, and port 1 and isolation ports are higher than 27.5, 35.1, and 30.5 dB, respectively. In the single-path mode with three states, the measured insertion losses are less than 1.13 dB; the measured isolations between transmission ports and isolation ports are higher than 28.8 dB, and the isolations between port 1 and isolation ports are higher than 28.2 dB at the design frequency.

Wireless Power Transfer Resonance Coupling Amplification by Load-Modulation Switching Controller

This paper proposes that transmitter-to-receiver resonator efficiency can be enhanced by the novel combination of resonator and switching controller at the receiver side. More specifically, the switching controller modulates the load resistance such that the receiver resonance is amplified. This increases the loaded-Q, reflected resistance, and, subsequently, overall efficiency and distance range. The efficiency and distance range are superior than resonator-only receivers, despite of losses from the switching controller itself. This breaks the common routine that typical switching converters only lower the power flow and efficiency when they are inserted in wireless power chain. Moreover, the scheme solves the common problem of load-variation-induced efficiency degradation. More specifically, if the present load value is deviated from optimal point, the proposed controller adjusts the effective load resistance to amplify the reflected resistance. The loaded-Q amplification is easily controlled simply by changing the duty ratio of switching controller. This is more feasible than traditional impedance transformation network whose control requires large array of capacitor-switch matrix or movement of coil position. The efficiencies with and without the switching-controlled resonance amplification are 60.2% and 51.7%, respectively, for a 20-W loading at 15-cm distance for a 20 cm × 16 cm receiver.