Impact Of Short-channel Effects Research Articles

On short channel effects in high voltage JFETs: A theoretical analysis

In this work, the impact of Short Channel Effects (SCEs), particularly Drain Induced Barrier Lowering (DIBL) on the performance of a high voltage Silicon Carbide (SiC) JFET has been thoroughly investigated. Drift-Diffusion simulations of on-state current-voltage characteristics and breakdown performance have been completed for different gate junction depths (xj) and mesa widths (MW). Due to the short channel length, realistic implant doping profiles extracted from experimentally calibrated Monte-Carlo based SRIM simulations have been used. Two suitable designs to eliminate premature DIBL-induced failure have been found: xj = 0.7 µm for MW=1.75 µm, and xj = 1 µm for MW=2 µm. We found that a 0.3 µm junction depth has a breakdown voltage of only 50 V due to collapse of the source-drain barrier at a relatively low drain bias. Threshold voltage (Vth) decreases with increasing junction depth, approaching 0 V. This is due to a combination of greater lateral straggling of implanted ions and improved electrostatic control of the channel. Our calculations demonstrate that the most robust option to mitigate DIBL and consequently early breakdown is to maintain xj≥1 µm. At this depth, the threshold voltage has a weak dependence on drain bias, indicating diminishing SCEs. Decreasing the mesa width mitigates early breakdown but requires a mesa width of less than 1.75 µm, which poses fabrication challenges.

Analog CMOS Design in Nanometer Regime

There is no doubt that the short-channel effects have affected the analysis and design of modern analog CMOS integrated circuits significantly. Thus, models that take into account these effects must be adopted in order to obtain more accurate results. In this paper, the AC small-signal low-frequency equivalent circuit of the short-channel MOSFET transistor is developed using an appropriate model. The impact of short-channel effects on the operation of basic building blocks of analog integrated circuits such as basic amplifier configurations, cascode stage, differential amplifier and composite transistor is investigated quantitatively. Additionally, the nonlinear distortion is investigated using the adopted model.

TCAD simulations of FDSOI devices down to deep cryogenic temperature

In this paper we demonstrate the feasibility of FDSOI device TCAD simulations down to deep cryogenic temperatures. To this purpose, Maxwell-Boltzmann carrier statistics is replaced by an analytical approximation for the Fermi-Dirac integral with 3D density of states. The device electrostatic is investigated by solving the Poisson equation in 2D, whereas the transport is simulated using the Drift-Diffusion model. We explore the impact of temperature on device performances in linear and saturation regions as well as the impact of short channel effects, accounted for various gate and spacer lengths, at room and deep cryogenic temperatures. Finally, the obtained results are compared to some experimental data, highlighting the role of TCAD simulations in providing insights in device physics and performances.

InGaAs MOSHEMT W-Band LNAs on Silicon and Gallium Arsenide Substrates

This letter presents the design, performance, and analysis of four low-noise amplifier (LNA) monolithic microwave integrated circuits (MMICs) operating in ${W}$ -band. Two LNA designs were fabricated in two variations of a 20-nm gate-length metal–oxide–semiconductor high-electron-mobility transistor (MOSHEMT) technology each. While for the first technology version the heterostructure is directly grown on the final gallium arsenide (GaAs) wafer, the second version uses direct wafer bonding to transfer the III–V heterostructure after the epitaxial growth to a silicon (Si) substrate. Based on the measured noise figure (NF) of the four MMICs over a comprehensive set of bias conditions, the impact of short-channel effects on the RF performance and possible improvements are analyzed. The first LNA covers an octave bandwidth with more than 15 dB of gain and an average NF (75–105 GHz) of 3.5 dB on a Si substrate. At 80 GHz, the second amplifier exhibits minimal NFs of 2.3 and 2.5 dB on GaAs and Si substrates, respectively. Compared to previously reported MOS- or Si-based technologies, the presented LNAs demonstrate state-of-the-art noise performance emphasizing the importance of electron confinement for highly scaled transistor technologies.

A closed loop inductorless equalizer with a modified analysis of power comparator behaviour

SummaryInductorless circuits are gaining advantage in radio frequency (RF) and high‐speed serial link circuits due to the reduced silicon area. This paper presents an inductorless adaptive analog equalizer using an adaptive hybrid filter comprising integrated low pass and high pass filter. The equalizer, designed and fabricated in 180‐nm CMOS technology, is able to adjust the high‐frequency boost (HFB) and cutoff frequency of the internal filters depending on the data rate and the channel loss. The presented equalizer operates at data rates more than 4 Gbps in post‐layout simulation without electrostatic discharge (ESD) and package parasitics. For the test purposes, the equalizer has been packaged in QFN 64 pin package and hence the measurement results are up to 3.125 Gbps. The measurement results show that the equalizer is able to adapt the HFB for the channel losses as high as 5 dB. Average dissipated power of the equalizer at 3.125 Gbps is 18 mW with 1.8‐V supply. After reading this chapter you should be able to understand the merits of the proposed hybrid filter compared with the conventional RC filters in the adaptive equalizer using spectrum balancing technique; theoretical analysis and the impact of short channel effects on the performance of the power comparator; and test results of the adaptive equalizer using the proposed hybrid filter in the spectrum balancing technique.

Large-Signal DG-MOSFET Modelling for RFID Rectification

This paper analyses the undoped DG-MOSFETs capability for the operation of rectifiers for RFIDs and Wireless Power Transmission (WPT) at microwave frequencies. For this purpose, a large-signal compact model has been developed and implemented in Verilog-A. The model has been numerically validated with a device simulator (Sentaurus). It is found that the number of stages to achieve the optimal rectifier performance is inferior to that required with conventional MOSFETs. In addition, the DC output voltage could be incremented with the use of appropriate mid-gap metals for the gate, as TiN. Minor impact of short channel effects (SCEs) on rectification is also pointed out.

Comparative Analysis of Mechanical Strain and Silicon Film Thickness on Charge Collection Mechanisms of Nanometer Scaled SOI Devices Under Heavy Ion and Pulsed Laser Irradiation

We investigate the impact of performance boosters using mechanical stress on the Single-Event Transient (SET) response of nanometer scaled Fully-Depleted Silicon-On-Insulator (SOI) devices. Laser SET measurements show that the active silicon layer thickness is the most important contributor to the SET response of highly scaled Ultra-Thin SOI (UTSOI) devices compared to the impact of strain. This is then demonstrated by dedicated TCAD calculations performed without taking into account any strain engineering technique. Finally, heavy ion-induced charge collection mechanisms are analyzed through the measurement of fast transients to get additional insights into the impact of short channel effects on the SET response of nanometer scaled SOI devices.