Abstract
This letter presents the design, performance, and analysis of four low-noise amplifier (LNA) monolithic microwave integrated circuits (MMICs) operating in ${W}$ -band. Two LNA designs were fabricated in two variations of a 20-nm gate-length metal–oxide–semiconductor high-electron-mobility transistor (MOSHEMT) technology each. While for the first technology version the heterostructure is directly grown on the final gallium arsenide (GaAs) wafer, the second version uses direct wafer bonding to transfer the III–V heterostructure after the epitaxial growth to a silicon (Si) substrate. Based on the measured noise figure (NF) of the four MMICs over a comprehensive set of bias conditions, the impact of short-channel effects on the RF performance and possible improvements are analyzed. The first LNA covers an octave bandwidth with more than 15 dB of gain and an average NF (75–105 GHz) of 3.5 dB on a Si substrate. At 80 GHz, the second amplifier exhibits minimal NFs of 2.3 and 2.5 dB on GaAs and Si substrates, respectively. Compared to previously reported MOS- or Si-based technologies, the presented LNAs demonstrate state-of-the-art noise performance emphasizing the importance of electron confinement for highly scaled transistor technologies.
Highlights
I N RECENT years, the gate-length scaling of Schottkybased high-electron-mobility transistor (HEMT) technologies reached fundamental limitations with feature sizes of 20–25 nm [1], [2] where a further performance improvement seems hardly feasible
Each of the four monolithic microwave integrated circuits (MMICs) is individually biased for an optimum noise figure (NF)
This letter presents the analysis and performance of four W -Band low-noise amplifier (LNA) MMICs that are fabricated in two variations of a 20-nm gate-length InGaAs metal–oxide–semiconductor high-electronmobility transistor (MOSHEMT) technology
Summary
I N RECENT years, the gate-length scaling of Schottkybased high-electron-mobility transistor (HEMT) technologies reached fundamental limitations with feature sizes of 20–25 nm [1], [2] where a further performance improvement seems hardly feasible. A major challenge of the gatelength scaling is the simultaneously inevitable reduction of the Schottky barrier thickness to keep control over the 2-D electron gas (2DEG). This provokes an exponential increase of the gate-leakage current. The electron confinement is, improved by employing direct wafer bonding of the III–V heterostructure to a silicon (Si) substrate. We further investigate the electron confinement of a 20-nm gate-length MOSHEMT technology by comparing the low-noise performance of MOSHEMTs on Si and GaAs substrates. For the technology version on GaAs substrates, the heterostructure is directly grown by molecular-beam epitaxy on 100-mm GaAs wafers.
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