Immersion Lithography Research Articles

Patterning of 25 nm Contact Holes at 90 nm Pitch: Combination of Line/Space Double Exposure Immersion Lithography and Plasma-Assisted Shrink Technology

In this work, two methods are combined in order to provide 25 nm contact holes at 90 nm pitch: the line/space double exposure immersion lithography and the plasma-assisted shrink technology. We first present the line/space imaging method with negative tone development to create directly 45 nm CH at 90 nm pitch. Then, we discuss plasma-assisted shrink technology and how it applies to these small contacts. Plasma-assisted shrink technology relies on running a fast cyclic process, where plasma polymers are deposited on the photoresist mask, then subsequently redistributed over the features sidewalls, allowing in final a diameter reduction of approximatively 50%. Finally, for the metal-hard-mask patterning approach, the dielectric etch challenges driven by the dimensional scaling are analysed and discussed.

45-nm silicon-on-insulator CMOS technology integrating embedded DRAM for high-performance server and ASIC applications

The 45-nm technology, called 12S and developed for IBM POWER7®, is an extremely robust and versatile technology platform that allows for a rich set of features that include embedded dynamic random access memory (DRAM), performance and dense static RAM (SRAM), a trench-based decoupling capacitor, a comprehensive device menu, and a high-performance hierarchical back-end interconnect scheme, all built on a silicon-on-insulator (SOI) substrate. Embedded DRAM was implemented for production in high-performance SOI for the first time and allowed us to leapfrog two generations of conventional SRAM densities. Immersion lithography was also employed for the first time in 45-nm IBM products. Our 45-nm design point represents a judicious leverage of silicon oxynitride dielectrics, scaled device technology, and rich features to yield chip-level performance enhancement of more than 50%, compared with our 65-nm node at comparable or less power. This paper describes the salient features of this technology node, the process architecture, the device design rationale, and the process design interactions.

Guest Editorial Special Section on the Advanced Semiconductor Manufacturing Conference

This special section of the IEEE TRANSACTIONS ON Semiconductor Manufacturing (TSM) provides a wider dissemination of selected material presented at the 2010 ASMC to the semiconductor manufacturing community. One paper discusses the structural and electrical characterization of ALD-deposited high-k films. Defects are studied in three papers from different perspectives; one focuses on a library of different types of defects, the second studies failure rate estimation of each process layer using critical area analysis and failing bit results, while the third reduces the electrostatically adhered particles on wafer backside by using ionizers. Lithography applications are discussed in one paper, where bright field defect inspection is employed for process window centering at the 22 nm node, and in another where topcoat-less resists are evaluated for high volume immersion lithography. One paper details the neural networks for advanced process control while another investigates yield improvement using a scalable parametric measurement macro. Finally, rule induction for identifying multilayer tool commonalities is evaluated.

Cost of Ownership/Yield Enhancement of High Volume Immersion Lithography Using Topcoat-Less Resists

The complexity and extra cost associated with a resist topcoat (TC) layer has motivated the industry to transition to TC-less resist processes. By switching to TC-less resists, track suppliers are able to achieve higher throughput using less costly equipment, scanner suppliers can increase the scanning speed of their litho systems with minimized risk of defects, and end users eliminate a process step and gain increased output at a lower cost. These factors become increasingly critical as a result of the heightened processing complexities associated with double patterning lithography. In addition to reduction in process complexity benefits, a TC-less process must also satisfy the other critical performance criteria, and results for overlay, autofocus, and imaging will be discussed. To justify transition to a new process, there also should be demonstration of associated cost reduction or productivity improvements.

Split, overlap, stitching, and process design for double patterning considering local reflectivity variation by using rigorous three-dimensional wafer-topography and lithography simulation

Double patterning (DP) was investigated for logic layout by using a rigorous three-dimensional (3D) wafer-topography/lithography simulator with water immersion lithography. With increasing complexity of the DP process, the 3D wafer-topography effect of stack structure must be considered, because of its impact to lithography. The main purpose of this paper is to present how to optimize both process and design to ensure overlap and connectivity of split patterns by solving electro-magnetic field distribution in wafer substrate, as well as resist region. A process window was analyzed varying not only focus, dose, and split masking layers, but also considering topography of substrate stack structures, which cause local reflectivity variations. Arbitrary 45 nm logic layout including an L-shaped pattern was analyzed. The process window of the second litho step was analyzed. Due to the reflection from the hard mask (HM, result of the first litho step), the process window was restricted and became smaller. The other option suggests that swapping the first and second litho masks is a better choice, with respect to the impact of wafer topography. The optimization of the stack process condition was analyzed by using the contour plot of reflectivity, as functions of n, k, and thickness of materials inside the bottom anti-reflective coating. The concept of extended normalized image log slope considering local reflectivity variation from wafer process is able to explain the variation of resist sidewall slope and exposure latitude.Therefore, it is useful to analyze connectivity at the stitching point by using a 3D wafer-topography/lithography simulator and to optimize the combination of the DP process and layout stitching design. Furthermore, as a design of an advanced process, litho-develop litho-etch was simulated.

Double Patterning Using Multilayer Hard Mask Process with Perhydropolysilazane

A new technology called the double patterning (DP) process with ArF immersion lithography is one of the candidate fabrication technologies for 32-nm-node devices. Over the past few years, many studies have been conducted on techniques of the DP process. Among these technologies, the double Si hard mask (HM) process is thought to be the most applicable technology from the viewpoint of high technical applicability to 32-nm-node device fabrication. However, this process has a disadvantage in terms of cost performance compared with other DP technologies since these HMs are formed by the chemical vacuum deposition (CVD) method. In this study, we examined the DP process using a dual spin-on Si-containing layer without using the CVD method to improve process cost and process applicability. Perhydropolysilazane (PSZ) was used as one of the middle layers (MLs). PSZ changes to SiO2 through reaction with water by the catalytic action of amine in the baking step. Using PSZ and Si-BARC as MLs, we succeeded in fabricating a fine pattern by this novel DP technique. In this paper, the issues and countermeasures of the double HM technique using spin-on Si-containing layers will be reported.

Evaluation of 193 nm Photoresist Material at Advanced Immersion Nodes

As 193 nm immersion lithography under single exposure moves toward the limit of 38 nm half pitch, more and more understanding has been achieved in the illumination. With the availability of same exposure tool and illumination condition, the key to the successful development of the photolithographic process will weigh toward good choice of and good process condition for the photoresist. Though different approaches exist for the evaluation of photoresists among major industrial players, the key understanding of the resist material has converged to some conservation quantity, which related to spatial resolution, line edge roughness, and resist sensitivity (RLS). Such quantity seems to be related to the formulation of modern chemically amplified photoresist. Although it is well-known that usual 193 nm photoresists needs a top coating for exposure tools that need water immersion since the water will interact with the acid that is created by photo-chemical reactions and caused patterning failure, recently, topcoat-less photo resist process was developed for immersion lithography with a small amount of additives blended into the conventional resist material. The availability of such resist has simplified the resist process and saved process cost, but may make the resist material more complicated. We have explored a number of normal immersion and topcoat-less immersion photoresists in the limit of 193 nm immersion lithography. We will present our data in the study of RLS and the resist profile.

Limit of Line End Shortening Correction under Single Exposure in 193 nm Immersion Lithography

As the lithography starts to approach the limit of 193 nm immersion imaging capability under single exposure, successful development of a lithographic process rely on the good balance of the process parameters, such as the exposure latitude and depth of focus for the dense, semi-dense, isolated structures, MEF, LWR, proximity bias, etc. Such balance requires very good understanding of the inter-relationship among them and ways to give reasonable specification to the important materials such as photoresist and photomasks. Although, relatively speaking, 1-dimensional structures, such as, line and space or even square contacts are relatively easy to understand and model with accurate simulations, which is close to perfect, 2-dimensional structures are not easy to understand physically and the simulation for them are up to larger errors. Since previous study on this subject was either done at larger ground-rules or lack of good physical understanding in the simulation, this paper will use both experimental wafer measurement data and physical modeling to probe the limits for the OPC correction of line (or space) end shortening structures at around 50 nm dimensions. Several structures will be studied in theory and wafer data.

Extension Use of Immersion Lithography for the 22nm Half-Pitch and Beyond

In double patterning process, exposure tools are required for better accuracy and productivity. NSR-S620D, which is Nikon immersion scanner, meets these requirements. This paper discusses the current status of Nikon immersion scanner and possibility to extend use of immersion lithography for the 22nm half-pitch and beyond

Full 3D-3C velocity measurement inside a liquid immersion droplet

We describe a tomographic PIV system for the measurement of the internal flow in a droplet over a stagnant and a moving surface. The flow condition is representative of the flow in an immersion droplet applied in a liquid immersion lithography machine. We quantify the accuracy and reliability of the measurements and compare the shape of the reconstructed measurement volume to shape measurements by means of shadowgraphy. First results indicate the internal flow pattern near the receding contact line, showing a small recirculation region.

Effect of upper surface characteristics on meniscus stability in immersion flow field

Liquid loss occurs at the receding contact line when scanning at high speeds resulting in defects on printed patterns in immersion lithography. To offer intuitive insights into the dynamic effects of the fluid confined between the lens and substrate on critical scan speeds, image processing techniques are explored to develop dynamic models for optimizing future designs of immersion units. Since the distance between the last lens and wafer is less than 1mm, the dynamic characteristics of the liquid (with free boundary and characteristics of the upper surface of the flow field) play an important role in liquid control, which is concerned in various potential immersion unit designs. A method for characterizing the meniscus dynamics is developed to analyze the liquid behavior and meniscus stability in immersion lithography. A second-order system model is presented to better understand the meniscus development during scanning motion. Experimental results have shown that the meniscus adhering to the hydrophilic surface allows for a higher scanning speed than that adhering to the hydrophobic surface.

Lens distortion for liquid renovation in immersion lithography

Liquid renovation is perhaps the best method to reduce contamination in immersion lithography, but it brings lens distortion because of the high density and viscosity of the immersion liquids compared to air. In this paper, considering wafer scanning, the three-dimensional computational liquid dynamics model and finite-element model are developed to investigate the lens distortion for immersion liquid renovation. After analyzing the influence of wafer scanning directions, the empirical formulas of the lens distortion for three-dimensional model are established to describe the effect of the parameters of lens and polymer which are used to mount lens and the parameters of immersion liquid flow on lens distortion.

Receding contact lines: From sliding drops to immersion lithography

Instabilities of receding contact lines often occur through the formation of a corner with a very sharp tip. These dewetting structures also appear in the technology of Immersion Lithography, where water is put between the lens and the silicon wafer to increase the optical resolution. In this paper we aim to compare corners appearing in Immersion Lithography to those at the tail of gravity driven-drops sliding down an incline. We use high speed recordings to measure the dynamic contact angle and the sharpness of the corner, for varying contact line velocity. It is found that these quantities behave very similarly for Immersion Lithography and drops on an incline. In addition, the results agree well with predictions by a lubrication model for cornered contact lines, hinting at a generic structure of dewetting corners.

Circular apertures for contact hole patterning in 193 nm immersion lithography

Contact hole patterning has always been one of the most challenging issues in lithography. Conventional optical proximity correction (OPC) approach for contact hole patterning involves dimensional biasing, addition of serifs at corners, and insertion of subresolution enhancement features. However, as dimensions reduce, process window enhancement resulted from conventional OPC approach encounters limitations. In this paper, a new approach for contact hole patterning is investigated. Instead of using a square shape as target of a printed feature, a circular shape is proposed. Using the proposed method improvement in aerial image quality is achieved and the average improvement in the depth of focus is around 11%. In addition, the average normalized image logarithmic slope improvement for different pitches is found to be around 15%.

Contact line dynamics of a superhydrophobic surface: application for immersion lithography

The dynamic contact line behavior of water on nanotextured rough hydrophobic and superhydrophobic surfaces is studied and contrasted to smooth hydrophobic surfaces for application in immersion lithography. Liquid loss occurs at the receding meniscus when the smooth substrate is accelerated beyond a critical velocity of approximately 1 m/s. Nanotexturing the surface with average roughness values even below 10 nm results in critical velocity larger than 2.5 m/s, the upper limit of the apparatus. This unexpected increase in critical velocity is observed for both sticky hydrophobic and slippery superhydrophobic surfaces. The authors attribute this large increase in critical velocity both in increased receding contact angle and in increased slip length for such nanotextured surfaces.

Experimental analysis of solid immersion interference lithography based on backside exposure technique

We report a method of fabricating metal nano-grating by Solid immersion Interference lithography based on Backside exposure technique (SIB). Solid immersion lithography can improve the resolution of interference patterns by a factor of n (refractive index of prism), and backside exposure technique can improve the energy utilization ratio and protect the surface of the resist from being contaminated. In the process of fabrication, a high quality sacrificial layer (dielectric grating with high modulation depth and appropriate duty ratio) is important for transferring the patterns to the metal film. We optimized the exposure/development time by simulating the process of backside exposure. Simulation and experiment results show that: using 441.6nm wavelength laser, a series of subwavelength patterns (used as sacrificial layer) with high modulation depth and appropriate duty ratio can be gotten, the feature size of the patterns can be down to 80nm which is less than 0.18λ. Using optimized condition, high quality sacrificial layer can be achieved by using the backside exposure technique. Backside exposure technique has a greater exposure/development time tolerance for fabricating nano-patterns than the conventional interference lithography, which can be used for nano-metal grating fabrication.

Simulation and Experimental Investigation of Immersion Flow Field in Immersion Lithography

Immersion lithography is the only actual applied technology for up to 45-mm IC production line.The high refractive index liquid filled between the last one projective lens and wafer is used to improve the optical resolution of the immersion lithography,but the photoresist leaching and liquid heating can occur during immersion exposure process.The liquid renovation must be considered in the immersion lithography because of its ability of pollution elimination and heat dispersion.A CFD model is established to study the influence of structural parameters on the updating efficiency of immersion flow field.The visual flow field test system composed of high-speed camera and data acquisition instrument is used to carry out the research of visualization of immersion flow field,and which is compared with the simulation result,thereby a set of optimized parameters of injection and recovery ports is obtained.

Synthesis and Evaluation of Adamantane-Containing Fluorinated Block Copolymers for Resist Modifers in Immersion Lithography

Synthesis and Evaluation of Adamantane-Containing Fluorinated Block Copolymers for Resist Modifers in Immersion Lithography

Material Development for ArF Immersion Resist Extension

ArF immersion process is being widely applied for advanced device manufacturing. ArF immersion lithography can cover 4x nm hp lithography. In addition, double patterning process allows extendibility towards 2x nm hp lithography. From the point of view of photoresist, it is utterly important for materials to bring out the maximum performance of ArF immersion process. In this study, we focused on photoresist development and substrate optimization, demonstrating good lithographic performance of sub-40nm hp resolution with well controlled line width roughness (LWR).First of all, we studied photo acid generator (PAG) behavior focusing on shortening acid diffusion length during Post Exposure Bake (PEB). Secondly, high dissolution contrast polymers in which dissolution properties are changed by acid catalyzed reaction through exposure and PEB are being studied. Thirdly, reflectivity control from substrate through optimization of light intensity over resist film thickness has been carried out. In this report, we have achieved 36.5nm line and space (LS) resolution with LWR of less than 10% of patterned critical dimension (CD). This achievement is very useful especially when utilized in combination with process tricks such as multiple patterning for extending existing ArF immersion lithography towards sub-20nm hp lithography.

Bottom-Anti-Reflective Coatings (BARC) for LFLE Double Patterning Process

Double patterning process with ArF immersion lithography has been developed as one of the most promising candidate for hp32 node and beyond. However complicated process flow and cost of ownership are the critical issue for this process. LELE (Litho-Etch-Litho-Etch) is the one of the standard process, but in order to reduce the process and cost, that LFLE(Litho-Freezing-Litho-Etch) and LLE (Litho-Litho-Etch) process have been investigated as the alternative process. In these processes, Organic Bottom-Anti-Reflective coating (BARC) is used two times with same film in both 1st Litho and 2nd Lithography process. In 2nd Lithography process, resist pattern will be printed at space area where exposed and developed in 1st lithography process. Therefore, organic BARC needs to have process stability in Photo and development step to keep good litho performance between 1st and 2nd lithography in LFLE / LLE process. This paper describes the process impact of 1st exposure and development for organic BARC, and the LFLE / LLE performance with optimized organic BARC will be discussed.