Sensing Image Processing Research Articles

Photon-number-resolving megapixel image sensor at room temperature without avalanche gain

In several emerging fields of study such as encryption in optical communications, determination of the number of photons in an optical pulse is of great importance. Typically, such photon-number-resolving sensors require operation at very low temperature (e.g., 4 K for superconducting-based detectors) and are limited to low pixel count (e.g., hundreds). In this paper, a CMOS-based photon-counting image sensor is presented with photon-number-resolving capability that operates at room temperature with resolution of 1 megapixel. Termed a quanta image sensor, the device is implemented in a commercial stacked (3D) backside-illuminated CMOS image sensor process. Without the use of avalanche multiplication, the 1.1 μm pixel-pitch device achieves 0.21e− rms average read noise with average dark count rate per pixel less than 0.2e−/s, and 1040 fps readout rate. This novel platform technology fits the needs of high-speed, high-resolution, and accurate photon-counting imaging for scientific, space, security, and low-light imaging as well as a broader range of other applications.

Characterisation of a novel reverse-biased PPD CMOS image sensor

A new pinned photodiode (PPD) CMOS image sensor (CIS) has been developed and characterised. The sensor can be fully depleted by means of reverse bias applied to the substrate, and the principle of operation is applicable to very thick sensitive volumes. Additional n-type implants under the pixel p-wells, called Deep Depletion Extension (DDE), have been added in order to eliminate the large parasitic substrate current that would otherwise be present in a normal device. The first prototype has been manufactured on a 18 μm thick, 1000 Ω .cm epitaxial silicon wafers using 180 nm PPD image sensor process at TowerJazz Semiconductor. The chip contains arrays of 10 μm and 5.4 μm pixels, with variations of the shape, size and the depth of the DDE implant. Back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v, and characterised together with the front-side illuminated (FSI) variants. The presented results show that the devices could be reverse-biased without parasitic leakage currents, in good agreement with simulations. The new 10 μm pixels in both BSI and FSI variants exhibit nearly identical photo response to the reference non-modified pixels, as characterised with the photon transfer curve. Different techniques were used to measure the depletion depth in FSI and BSI chips, and the results are consistent with the expected full depletion.

High Conversion-Gain Pinned-Photodiode Pump-Gate Pixels in 180-nm CMOS Process

This paper presents the design and characterization of high conversion-gain pixels in a 180-nm CMOS image sensor process. By reducing overlapping capacitance between a floating diffusion and transfer gate, output-referred pixel conversion gain as high as 118uV/e- and read noise as low as 1.8e- rms are experimentally achieved without significant lag. A dark current of 38 pA/cm2 is measured at 60 °C. Comparison between the proposed devices and a baseline pixel regarding device structure and characterization results is also presented.

High-Resolution Real-Time Visual Inspection System for Micro Assembly

For precise assembly of miniature parts, the precise inspection for parts’ posture and real-time servo control for assembly greatly depend on the performance of visual inspection system. This paper proposed a high-resolution real-time visual inspection system of micro assembly. The CMOS image sensor and high-speed digital signal processing chip were chosen to design the image acquisition module, image processing module and image display module. High-accuracy display on the common display device was implemented with the video encoding chip and FPGA. The test results showed that the processing speed with preprocessing could reach 3.5 frames per second with 5 mega-pixel resolution, and the display accuracy after threshold processing had little loss. Micro parts assembly experiment and high accuracy Peg-in-Hole assembly experiment are done to test the performance of the proposed visual inspection system. This visual inspection system can be used for high-resolution real-time micro assembly and other real-time visual servo control.

A Dual-Imaging Speed-Enhanced CMOS Image Sensor for Real-Time Edge Image Extraction

This paper presents a CMOS image sensor (CIS) that extracts a multi-level edge image as well as a human-friendly normal image in a real time from conventional pixels for machine-vision applications, utilizing a proposed speed/power-efficient dual-mode successive-approximation register analog-to-digital converter (SAR ADC). The proposed readout scheme operates in two modes, fine step SAR (FS-SAR) mode and coarse-step single-slope (CS-SS) mode, depending on the difference ( $\Delta $ ) between a chosen pixel and the previous pixel. If a chosen pixel is at a boundary of an object with a large $\Delta $ from the previous pixel, the readout ADC works in the CS-SS mode to readout the edge strength (ES), while the FS-SAR mode is applied for other pixels. By displaying the ES, a multi-level edge image can be obtained in a real time along with a normal image with no hardware/time overhead. By saving the MSBs conversion cycles regardless of $\Delta $ , the proposed dual-mode readout scheme enhances the readout speed and reduces power consumption. A prototype QQVGA CIS with 10-bit SAR ADCs was fabricated in a 0.18- $\mu \text{m}$ 1P4M CMOS image sensor process with a 4.9- $\mu \text{m}$ pixel pitch. With a maximum pixel rate of 61.4 Mp/s, the prototype demonstrated figure of merits of 70 pJ/pixel/frame, 0.35 $\text{e}^{-}\cdot \text {nJ}$ , and 0.34 $\text{e}^{-}\cdot \text {pJ}$ /step.

A process modification for CMOS monolithic active pixel sensors for enhanced depletion, timing performance and radiation tolerance

For the upgrade of its Inner Tracking System, the ALICE experiment plans to install a new tracker fully constructed with monolithic active pixel sensors implemented in a standard 180 nm CMOS imaging sensor process, with a deep pwell allowing full CMOS within the pixel. Reverse substrate bias increases the tolerance to non-ionizing energy loss (NIEL) well beyond 10131MeVneq∕cm2, but does not allow full depletion of the sensitive layer and hence full charge collection by drift, mandatory for more extreme radiation tolerance. This paper describes a process modification to fully deplete the epitaxial layer even with a small charge collection electrode. It uses a low dose blanket deep high energy n-type implant in the pixel array and does not require significant circuit or layout changes so that the same design can be fabricated both in the standard and modified process. When exposed to a 55Fe source at a reverse substrate bias of −6 V, pixels implemented in the standard and the modified process in a low and high dose variant for the deep n-type implant respectively yield a signal of about 115 mV, 110 mV and 90 mV at the output of a follower circuit. Signal rise times heavily affected by the speed of this circuit are 27.8+∕−5 ns, 23.2+∕−4.2 ns, and 22.2+∕−3.7 ns rms, respectively. In a different setup, the single pixel signal from a 90Sr source only degrades by less than 20% for the modified process after a 10151MeVneq∕cm2 irradiation, while the signal rise time only degrades by about 16+∕−2 ns to 19+∕−2.8 ns rms. From sensors implemented in the standard process no useful signal could be extracted after the same exposure. These first results indicate the process modification maintains low sensor capacitance, improves timing performance and increases NIEL tolerance by at least an order of magnitude.

Brief Analysis of Image Signal Processing for Smart Phone

The imaging quality of camera phone is mainly determined by the lens, CMOS image sensor(CIS for short) and image signal processing(ISP for short),the algorithm of ISP is especially important because the thickness of the CIS is greatly restricted as cellphones tend to be thinner and lighter. The main function of ISP is to do the linearization, lens shading, bad pixel correction, color interpolation, AUTO white balance, color correction, gamma correction, de-noising and sharpening to make the digital images closer to the reality scene. In view of the importance of ISP in the imaging system of camera phone, deep research on it has theoretical significance and market value.

Fully Depleted Pinned Photodiode CMOS Image Sensor With Reverse Substrate Bias

A new pixel design using fully depleted pinned photodiode (PPD) in a 180-nm CMOS image sensor (CIS) process has been developed and the first experimental results from a test chip are presented. The sensor can be fully depleted by means of reverse bias applied to the substrate, and the principle of operation is applicable to very thick sensitive volumes. Additional n-type implants under the in-pixel p-wells have been added to the manufacturing process in order to eliminate the large parasitic substrate current that would otherwise be present in a normal device. The new design shows the same electro-optical performance as the PPD pixel it is based on, and can be fully depleted without significant leakage currents. This development has the potential to greatly increase the quantum efficiency of scientific PPD CIS at near-infrared and soft X-ray wavelengths.

Image Processing Color Model Techniques and Sensor Networking in Identifying Fire from Video Sensor Node

Image Processing Color Model Techniques and Sensor Networking in Identifying Fire from Video Sensor Node

Investigation of CMOS pixel sensor with 0.18 μm CMOS technology for high-precision tracking detector

The Circular Electron Positron Collider (CEPC) proposed by the Chinese high energy physics community is aiming to measure Higgs particles and their interactions precisely. The tracking detector including Silicon Inner Tracker (SIT) and Forward Tracking Disks (FTD) has driven stringent requirements on sensor technologies in term of spatial resolution, power consumption and readout speed. CMOS Pixel Sensor (CPS) is a promising candidate to approach these requirements. This paper presents the preliminary studies on the sensor optimization for tracking detector to achieve high collection efficiency while keeping necessary spatial resolution. Detailed studies have been performed on the charge collection using a 0.18 μm CMOS image sensor process. This process allows high resistivity epitaxial layer, leading to a significant improvement on the charge collection and therefore improving the radiation tolerance. Together with the simulation results, the first exploratory prototype has bee designed and fabricated. The prototype includes 9 different pixel arrays, which vary in terms of pixel pitch, diode size and geometry. The total area of the prototype amounts to 2 × 7.88 mm2.

A Tileable CMOS X-Ray Line Detector Using Time-Delay-Integration With Pseudomultisampling for Large-Sized Dental X-Ray Imaging Systems

This paper presents a low-power and low-noise tileable CMOS X-ray line detector with time-delay-integration (TDI) for large-sized dental X-ray imaging systems. The proposed X-ray line detector with TDI adopts pseudomultisampling (PMS) using shifted clocks for the single-slope analog-to-digital converter (ADC) to reduce the required clock cycles for the ADC. The reduced clock cycle decreases the dynamic power and power fluctuation to ensure power stability for large-sized X-ray detectors. The TDI X-ray line detector with PMS was fabricated using 0.18- $\mu \text{m}$ CMOS image sensor process technology with a stitching process, which has an image format of 1010 $\times $ 86 and a pixel size of $75\,\,\mu \text{m}\,\,\times 75\,\,\mu \text{m}$ . The X-ray line detectors are tiled with $1 \times 2$ and $1\,\,\times3$ arrays to enlarge the active areas for dental panoramic and cephalometric X-ray imaging systems, respectively. The measurement results show the random noise of 0.43 LSB and a dynamic range of 78.5 dB, when the number of TDI stages is 86 and the number of PMS steps is 4. The dynamic current and power consumption per ADC are reduced from 157.4 $\mu \text{A}$ and $283.32~\mu \text{W}$ to $41.2~\mu \text{A}$ and 74.16 $\mu \text{W}$ , respectively, when PMS is adopted for TDI.

Analytical Modeling and TCAD Simulation of a Quanta Image Sensor Jot Device With a JFET Source-Follower for Deep Sub-Electron Read Noise

A novel quanta image sensor (QIS) jot device with a CMOS compatible junction-field effect transistor (JFET) source follower (SF) is introduced. The device is proposed to further reduce the read noise of QIS jots and ultimately realize a read noise of 0.15e-r.m.s. for accurate photoelectron counting. We take advantage of the small gate capacitance in a p-channel JFET SF to reduce the total capacitance of the floating diffusion, which yields a greatly improved conversion gain of 1.38 mV/e- in TCAD simulation compared to MOSFET SF with the same pitch size. Lower 1/ ${f}$ noise is also anticipated yielding a low input-referred read noise. The device is designed in a 45 nm CMOS image sensor process. The fundamental working principles of this device are discussed, and important functionalities are analyzed with simulation and theory.

Development of a 55 μm pitch 8 inch CMOS image sensor for the high resolution NDT application

A CMOS image sensor (CIS) with a large area for the high resolution X-ray imaging was designed. The sensor has an active area of 125 × 125 mm2 comprised with 2304 × 2304 pixels and a pixel size of 55 × 55 μm2. First batch samples were fabricated by using an 8 inch silicon CMOS image sensor process with a stitching method. In order to evaluate the performance of the first batch samples, the electro-optical test and the X-ray test after coupling with an image intensifier screen were performed. The primary results showed that the performance of the manufactured sensors was limited by a large stray capacitance from the long path length between the analog multiplexer on the chip and the bank ADC on the data acquisition board. The measured speed and dynamic range were limited up to 12 frame per sec and 55 dB respectively, but other parameters such as the MTF, NNPS and DQE showed a good result as designed. Based on this study, the new X-ray CIS with ∼ 50 μm pitch and ∼ 150 cm2 active area are going to be designed for the high resolution X-ray NDT equipment for semiconductor and PCB inspections etc.

Integrated visual sensor with 2D/3D imaging and in‐situ proximity sensing for mobile devices

A low-power visual sensor for low-light 2D imaging, proximity sensing, and 3D depth imaging is presented; it is applicable to smart sensing applications such as user recognition under dark conditions, gesture sensing, and extended user interface/user experience (UI/UX) in mobile devices. With integrated background suppression circuits, the sensor provides in-situ proximity sensing that generates a background-cancelled proximity map while capturing 2D images. In addition, 3D depth images are provided based on stereo matching with two 2D images from the visual sensor and the existing camera module. The prototype sensor was fabricated with a 0.11 μm 1P4M CMOS image sensor (CIS) process. The power consumption is 1.98 mW (at 15 fps) from the sensor and 9.38 mW (at 16 ms on-time) from the infrared LED.

Improvement to the signaling interface for CMOS pixel sensors

The development of the readout speed of CMOS pixel sensors (CPS) is motivated by the demanding requirements of future high energy physics (HEP) experiments. As the interface between CPS and the data acquisition (DAQ) system, which inputs clock from the DAQ system and outputs data from CPS, the signaling interface should also be improved in terms of data rates. Meanwhile, the power consumption of the signaling interface should be maintained as low as possible. Consequently, a reduced swing differential signaling (RSDS) driver was adopted instead of a low-voltage differential signaling (LVDS) driver to transmit data from CPS to the DAQ system. In order to increase the capability of data rates, a serial source termination technique was employed. A LVDS/RSDS receiver was employed for transmitting clock from the DAQ system to CPS. A new method of generating hysteresis and a special current comparator were used to achieve a higher speed with lower power consumption. The signaling interface was designed and submitted for fabrication in a 0.18µm CMOS image sensor (CIS) process. Measurement results indicate that the RSDS driver and the LVDS receiver can operate correctly at a data rate of 2Gb/s with a power consumption of 19.1mW.

A novel source–drain follower for monolithic active pixel sensors

Monolithic active pixel sensors (MAPS) receive interest in tracking applications in high energy physics as they integrate sensor and readout electronics in one silicon die with potential for lower material budget and cost, and better performance. Source followers (SFs) are widely used for MAPS readout: they increase charge conversion gain 1/Ceff or decrease the effective sensing node capacitance Ceff because the follower action compensates part of the input capacitance. Charge conversion gain is critical for analog power consumption and therefore for material budget in tracking applications, and also has direct system impact. This paper presents a novel source–drain follower (SDF), where both source and drain follow the gate potential improving charge conversion gain. For the inner tracking system (ITS) upgrade of the ALICE experiment at CERN, low material budget is a primary requirement. The SDF circuit was studied as part of the effort to optimize the effective capacitance of the sensing node. The collection electrode, input transistor and routing metal all contribute to Ceff. Reverse sensor bias reduces the collection electrode capacitance. The novel SDF circuit eliminates the contribution of the input transistor to Ceff, reduces the routing contribution if additional shielding is introduced, provides a way to estimate the capacitance of the sensor itself, and has a voltage gain closer to unity than the standard SF. The SDF circuit has a somewhat larger area with a somewhat smaller bandwidth, but this is acceptable in most cases.A test chip, manufactured in a 180nm CMOS image sensor process, implements small prototype pixel matrices in different flavors to compare the standard SF to the novel SF and to the novel SF with additional shielding. The effective sensing node capacitance was measured using a 55Fe source. Increasing reverse substrate bias from −1V to −6V reduces Ceff by 38% and the equivalent noise charge (ENC) by 22% for the standard SF. The SDF provides a further 9% improvement for Ceff and 25% for ENC. The SDF circuit with additional shielding provides 18% improvement for Ceff, and combined with −6V reverse bias yields almost a factor 2.

CMOS image sensor with lateral electric field modulation pixels for fluorescence lifetime imaging with sub-nanosecond time response

This paper presents the design and implementation of a time-resolved CMOS image sensor with a high-speed lateral electric field modulation (LEFM) gating structure for time domain fluorescence lifetime measurement. Time-windowed signal charge can be transferred from a pinned photodiode (PPD) to a pinned storage diode (PSD) by turning on a pair of transfer gates, which are situated beside the channel. Unwanted signal charge can be drained from the PPD to the drain by turning on another pair of gates. The pixel array contains 512 (V) × 310 (H) pixels with 5.6 × 5.6 µm2 pixel size. The imager chip was fabricated using 0.11 µm CMOS image sensor process technology. The prototype sensor has a time response of 150 ps at 374 nm. The fill factor of the pixels is 5.6%. The usefulness of the prototype sensor is demonstrated for fluorescence lifetime imaging through simulation and measurement results.

Charge collection and non-ionizing radiation tolerance of CMOS pixel sensors using a 0.18 μm CMOS process

The proposed Circular Electron Positron Collider (CEPC) will be primarily aimed for precision measurements of the discovered Higgs boson. Its innermost vertex detector, which will play a critical role in heavy-flavor tagging, must be constructed with fine-pitched silicon pixel sensors with low power consumption and fast readout. CMOS pixel sensor (CPS), as one of the most promising candidate technologies, has already demonstrated its excellent performance in several high energy physics experiments. Therefore it has been considered for R&D for the CEPC vertex detector. In this paper, we present the preliminary studies to improve the collected signal charge over the equivalent input capacitance ratio (Q/C), which will be crucial to reduce the analog power consumption. We have performed detailed 3D device simulation and evaluated potential impacts from diode geometry, epitaxial layer properties and non-ionizing radiation damage. We have proposed a new approach to improve the treatment of the boundary conditions in simulation. Along with the TCAD simulation, we have designed the exploratory prototype utilizing the TowerJazz 0.18μm CMOS imaging sensor process and we will verify the simulation results with future measurements.

A 256×256 time-of-flight image sensor based on center-tap demodulation pixel structure

This paper proposes a 256 $\\times$ 256 time-of-flight (TOF) image sensor based on the center-tap (CT) demodulation pixel structure. The image sensor can capture both the two-dimensional (2D) high speed image and the three-dimensional (3D) depth image. The CT pixel consists of two split pinned photodiode (PPD) regions and two pairs of transfer transistors. The transfer transistors adopt a non-uniform doped channel (NUDC) structure, which can increase the electron transfer speed along the transfer channel and eliminate the image lag for high speed imaging. The pixel size is 10 $\\upmu$m $\\times$ 10 $\\upmu$m, and we design the implementation process of the pixel to increase the electron transfer speed. The sensor is fabricated in a 0.18 $\\upmu$m 1P5M CMOS image sensor process. Test results show that it can capture the 430-fps intensity image and the 90-fps depth image in two different imaging modes. The rectified non-linearity within the 1.0--7.5 m depth measurement range achieves less than 3 cm, and the measurement accuracy achieves 4.0 cm at 2.5 m, corresponding to the relative error of 1.6\\%.

Front end optimization for the monolithic active pixel sensor of the ALICE Inner Tracking System upgrade

ALICE plans to replace its Inner Tracking System during the second long shut down of the LHC in 2019 with a new 10 m2 tracker constructed entirely with monolithic active pixel sensors. The TowerJazz 180 nm CMOS imaging Sensor process has been selected to produce the sensor as it offers a deep pwell allowing full CMOS in-pixel circuitry and different starting materials. First full-scale prototypes have been fabricated and tested. Radiation tolerance has also been verified. In this paper the development of the charge sensitive front end and in particular its optimization for uniformity of charge threshold and time response will be presented.