Sensing Image Processing Research Articles

Low-Power Optical Sensor for Traffic Detection

A CMOS sensor chip was used, together with an Arduino microcontroller, to create and verify a low-power low-cost optical motion detector for use in traffic detection under dark and daylight conditions. The chip can sense object features with very high dynamic range. On-chip near sensor image processing was used to reduce the data to be transferred to a host computer. A method using local extrema point detection was used to estimate motion through time-to-impact (TTI). Sensor data from the headlights of an approaching/passing car were used to extract TTI values similar to estimations from distance and speed of the object. The method can be used for detection of approaching objects to switch on streetlights (dark conditions) or sensors for traffic lights instead of magnetic sensors in the streets or conventional cameras (dark and daylight conditions). A sensor with a microcontroller operating at low clock frequency will consume less than 30 mW in this application.

A Low-power Extended-counting Delta-sigma ADC for CMOS Image Sensors

This paper presents an incremental delta sigma analog to digital converter (ADC) using an extended counting technique for CMOS image sensors. A modified extended counting method is proposed to reduce the over sampling ratio (OSR) and consequently increase conversion speed without increasing the hardware complexity. To further reduce the chip size and power consumption, a self-biased amplifier is shared between the adjacent stages of the delta-sigma modulator. The proposed ADC is fabricated in a 0.18-㎛ CMOS image sensor process and occupies 0.0026 ㎟. It achieves 65 ㏈ of signal noise and distortion ratio (SNDR) for a signal bandwidth of 156.25 ㎑ with a 20 ㎒ operating clock and consumes 45 μW from a 1.8 V power supply. The measured differential nonlinearity (DNL) and integral nonlinearity (INL) are +0.49 / −0.22 and +0.61 / −0.64 LSB (least significant byte), respectively.

An Ultra-Low Power PPG and mm-Resolution ToF PPD-Based CMOS Chip Towards All-in-One Photonic Sensors

This paper presents a CMOS photonic sensor covering multiple applications from ambient light sensing to time resolved photonic sensing. The sensor is made of an array of gated pinned photodiodes (PPDs) averaged using binning and passive switched-capacitor (SC) charge sharing combined with ultra-low-power amplification and analog-to-digital conversion. The chip is implemented in a 180 nm CMOS image sensor (CIS) process and features high sensitivity, low-noise and low-power performance. Measurement results demonstrate $\mu \text{W}$ health monitoring through Photoplethysmography (PPG), 10 ps resolution for time resolved light sensing and mm precision for time-of-flight (ToF) distance ranging obtained with a frame rate of 50 Hz and 20 dB ambient light rejection.

Active-Reset for the N+P Single-Ended SPAD Used in the NIR LiDAR Receivers

A monolithic resistorless circuit has been designed for active reset of the N+P single-ended (common anode) single-photon avalanche diode (SPAD). This type of SPAD has enhanced the photon detection efficiency in the near-infrared (NIR) region relatively to the P+N (two-ended) SPAD. Due to this fact, the N+P SPAD is a better candidate for the light detection and range (LiDAR) working in the NIR region. The circuit is fabricated in a standard 0.18- $\mu \text{m}$ CMOS image sensor process. The dead time after each photon detection is adjustable; the minimum measured value is 4 ns. The maximum photon count rate corresponding to this dead time is ${2.5}\cdot {10}^{{8}}$ photons/s. This circuit guarantees precise repeatable response, short and well-controlled dead time, and after-pulsing effect reduction. All these are essential for many SPAD applications and crucial for increasing the saturation level of the silicon photo multiplier (SiPM)-based LiDAR systems working in strong background light conditions on sunny day.

A 2.6 μW Monolithic CMOS Photoplethysmographic (PPG) Sensor Operating With 2 μW LED Power for Continuous Health Monitoring.

Photoplethysmography (PPG) enables wearable vitals monitoring. Nevertheless, it is still limited by the few mA of the LEDs driving current. We present a PPG sensor integrating an array of dedicated pinned-photodiodes (PPD) with a full readout chain integrated in a 0.18 μm CMOS Image Sensor (CIS) process. The sensor features a total input referred noise of 0.68 e-rms per PPD, independently of the input light, and achieves a 4.6 μW total power consumption, including the 2 μW LED power, at 1.38 bpm heart rate average error.

Preface

The 2019 3rd International Conference on Electrical, Mechanical and Computer Engineering (ICEMCE 2019) will be held on August 9-11, 2019 in Guizhou, China. The conference report reflects the current interest of the international and Chinese research community, such as Analysis of Power Quality and System Stability, Circuits and electronics, electro-optical phenomena of semiconductors, power electronics technology, remote control and techniques of GPS, smart grid, machinery and agriculture, machinery manufacturing and automation, mechanical engineering and mechanics, algorithms, Artificial intelligence, computer security, digital signal and image processing and wireless sensor networks. 2019 3rd International Conference on Electrical, Mechanical and Computer Engineering is a multi-disciplinary conference bringing together students, young researchers, postdoctoral and experienced researchers working in different research fields to promote the gathering and sharing of interests and achievements, so as to achieve better cooperation.The Conference work was carried out in 3 sections:● Electrical Engineering● Mechanical Engineering● Computer scienceCommittee memberList of Conference Chairs, Program Committee Co-chair, Local Chair, Advisory Committee, Technical Committee also available in this pdf.

Indirect Time-of-Flight Depth Sensor with Two-Step Comparison Scheme for Depth Frame Difference Detection.

A depth sensor with integrated frame difference detection is proposed. Instead of frame difference detection using light intensity, which is vulnerable to ambient light, the difference in depth between successive frames can be acquired. Because the conventional time-of-flight depth sensor requires two frames of depth-image acquisition with four-phase modulation, it has large power consumption, as well as a large area for external frame memories. Therefore, we propose a simple two-step comparison scheme for generating the depth frame difference in a single frame. With the proposed scheme, only a single frame is needed to obtain the frame difference, with less than half of the power consumption of the conventional depth sensor. Because the frame difference is simply generated by column-parallel circuits, no access of the external frame memory is involved, nor is a digital signal processor. In addition, we used an over-pixel metal–insulator–metal capacitor to store temporary signals for enhancing the area efficiency. A prototype chip was fabricated using a 90 nm backside illumination complementary metal–oxide–semiconductor (CMOS) image sensor process. We measured the depth frame difference in the range of 1–2.5 m. With a 10 MHz modulation frequency, a depth frame difference of >10 cm was successfully detected even for objects with different reflectivity. The maximum relative error from the difference of the reflectivity (white and wooden targets) was <3%.

Passive CMOS Single Photon Avalanche Diode Imager for a Gun Muzzle Flash Detection System

We present the architecture and design of a novel $64\times64$ CMOS single-photon avalanche diode (SPAD)-based imager for gun muzzle flash detection. The imager is fabricated in a standard front side illuminated $0.18~\mu \text{m}$ CMOS image sensor process. Each pixel comprises a $25~\mu \text{m}$ diameter SPAD, a variable-load passive quenching circuit implemented with 1.8 V PMOS, an 8-bit counter, an 8-bit latch register, and digital processing electronics, and feeds an 8-bit output bus. The array delivers two-dimensional intensity data through photon counting, with integration time as low as $5~\mu \text{s}$ over the full dynamic range. Per-pixel digital memory enables fully parallel processing and global-shutter mode readout. The imager can acquire fast optical events at high frame rate (up to 200 kfps) and at single-photon sensitivity. The imager has an 8-pixel (64-bit) parallel output bus. This imager enables for the first time the detection and arrival-direction determination of individual muzzle flashes in real time, and even in the case of bursts of flashes, at a moderate cost and size. The presented results confirm the feasibility of gun muzzle flash online detection in the visible or NIR spectrum by uncooled silicon SPAD detectors using standard CMOS technology.

Development Review of Novel Laparoscope Technology

The proportion of laparoscopic surgeries is continuously increasing in general surgeries. Along with the development and application, new image sensor and digital image processing technology accelerated the emergence of novel laparoscope in recent years. Stereoscopic laparoscope (3D) appearing make the space orientation more accurate. new imaging methods and new structure design satisfy more clinical requirements; combination with optical technology (NBI technique, PDD technique, ICG technique) make intraoperative diagnosis possible.

On the Image Sensor Processing for Lane Detection and Control in Vehicle Lane Keeping Systems.

Lane keeping systems for a keeping a vehicle in the desired lane is key to advanced driving assistance system in autonomous vehicles. This paper presents a cost-effective image sensor with efficient processing algorithm for lane detection and lane control applications to autonomous delivery systems. The algorithm includes (1) lane detection by inverse perspective mapping and random sample consensus parabola fitting and (2) lane control by pure pursuit steering controller and classical proportional integral speed controller based on a nonholonomic kinematic model. The image sensor experiments conducted on a 1/10 scale model car maneuvering in a straight–curve–straight lane validate the better processing performance before, during, and after the turning section over previous work. The image sensor with the processing algorithm achieves the average lane detection error within 5% and maximum cross-track error within 9% in real-time. The development shall pave the way to cost-effective autonomous delivery systems.

Quarter Video Graphics Array Digital Pixel Image Sensing With a Linear and Wide- Dynamic-Range Response by Using Pixel-Wise 3-D Integration

We have developed a quarter video graphics array (QVGA) digital pixel image sensor by using the 3-D integration technology. The pulse-frequency modulation (PFM) analog-to-digital converter (ADC) operates as a digital pixel, which overcomes the signal saturation due to the full well capacity of the photodiode (PD). We have also newly designed a PFM-ADC for pixels with a pinned PD and a floating diffusion to comply with the CMOS image sensor process used to attain high sensitivity and low noise. PDs, comparators, logic circuits, and counters are integrated into two silicon-on-insulator layers by pixel-wise 3-D integration with gold electrodes with a 5 μm diameter, thereby achieving a QVGA resolution for a 20-mm square chip in the 0.18and 0.2-μm process nodes. The developed sensor exhibits both the excellent linearity and a widedynamic range of more than 96 dB. Video images with a high bit depth of 16 bit are also obtained to demonstrate the superior image sensing, capable of capturing the real world at high fidelity.

Fully Integrated Light-Sensing Stimulator Design for Subretinal Implants.

This paper presents a fully integrated photodiode-based low-power and low-mismatch stimulator for a subretinal prosthesis. It is known that a subretinal prosthesis achieves 1600-pixel stimulators on a limited single-chip area that is implanted beneath the bipolar cell layer. However, the high-density pixels cause high power dissipation during stimulation and high fabrication costs because of special process technologies such as the complementary metal-oxide semiconductor CMOS image sensor process. In addition, the many residual charges arising from the high-density pixel stimulation have deleterious effects, such as tissue damage and electrode corrosion, on the retina tissue. In this work, we adopted a switched-capacitor current mirror technique for the single-pixel stimulator (SPStim) that enables low power consumption and low mismatch in the subretinal device. The customized P+/N-well photodiode used to sense the incident light in the SPStim also reduces the fabrication cost. The 64-pixel stimulators are fabricated in a standard 0.35-μm CMOS process along with a global digital controller, which occupies a chip area of 4.3 × 3.2 mm2 and are ex-vivo demonstrated using a dissected pig eyeball. According to measured results, the SPStim accomplishes a maximum biphasic pulse amplitude of 143 μA, which dissipates an average power of 167 μW in a stimulation period of 5 ms, and an average mismatch of 1.12 % between the cathodic and anodic pulses.

Hybrid approach for fruits quality prediction using image processing and sensors technique

The ability to recognise freshness of fruits and vegetables will be an incredible help for agriculturists to optimise the harvesting stage which abstains from reaping either under-developed or over-developed natural products. Techniques like image processing, near infrared spectroscopy (NIRS), sensors are used to predict the quality of fruits. Most of these mentioned techniques are costly and focused on external features of the fruits. Therefore, this paper presents a hybrid framework to predict the quality of fruits by combining image processing techniques and sensor setup. The proposed hybrid framework improves prediction accuracy rate by considering external as well as internal features of the fruit. Applying image preprocessing, 36 features are extracted from all banana samples. Among them, the most five influential features selected with the help of correlation matrix and linear regression. Simultaneously, with the help of multi-sensor setup, four influential gaseous features are extracted. K-means unsupervised learning algorithm applied on effective features of banana samples and their quality classified into three categories, such as Eatable, MaybeEatable, NotEatable. The implemented framework could classify banana fruit samples with approximately 95% accuracy.

Memetic Particle Gravitation Optimization Algorithm for Solving Clustering Problems

Data clustering is a well-known data analysis technique for organizing unlabeled datapoints into clusters on the basis of similarity measures. The real-world applications of data clustering include bioinformatics, vector quantization, data mining, geographical information systems, pattern recognition, image processing, and wireless sensors. The data in a cluster are similar (minimizing the intra-cluster distance) and differ from the data in other clusters (maximizing the inter-cluster distance). The cluster problem has been proven to be NP-hard, but can be solved using meta-heuristic algorithms, such as ant colony optimization, genetic algorithms, gravitational search algorithm (GSA), and particle swarm optimization (PSO). This paper proposes a memetic clustering algorithm with efficient search and fast convergence, respectively, based on PSO and GSA, called the memetic particle gravitation optimization (MPGO) algorithm. The two main mechanisms of MPGO are hybrid operation and diversity enhancement. The former involves the exchange of individuals from two subpopulations after a predefined number of function evaluations (FEs), whereas the latter involves an enhancement operator, which is similar to the crossover process of differential evolution, for enhancing the diversity of each system. Individuals from the PSO and GSA systems are selected for the exchange of solutions by using the roulette-wheel approach. The performance of the proposed algorithm was evaluated on 52 benchmark test functions, six UCI machine learning benchmarks, and image segmentation of six well-known images. A comparison with existing algorithms verified the superior performance of the proposed algorithm in terms of a fitness value, an accuracy rate, and a peak signal-to-noise ratio.

Hybrid approach for fruits quality prediction using image processing and sensors technique

The ability to recognise freshness of fruits and vegetables will be an incredible help for agriculturists to optimise the harvesting stage which abstains from reaping either under-developed or over-developed natural products. Techniques like image processing, near infrared spectroscopy (NIRS), sensors are used to predict the quality of fruits. Most of these mentioned techniques are costly and focused on external features of the fruits. Therefore, this paper presents a hybrid framework to predict the quality of fruits by combining image processing techniques and sensor setup. The proposed hybrid framework improves prediction accuracy rate by considering external as well as internal features of the fruit. Applying image preprocessing, 36 features are extracted from all banana samples. Among them, the most five influential features selected with the help of correlation matrix and linear regression. Simultaneously, with the help of multi-sensor setup, four influential gaseous features are extracted. K-means unsupervised learning algorithm applied on effective features of banana samples and their quality classified into three categories, such as Eatable, MaybeEatable, NotEatable. The implemented framework could classify banana fruit samples with approximately 95% accuracy.

In-Pixel Aperture CMOS Image Sensor for 2-D and 3-D Imaging

This paper presents a CMOS image sensor with the in-pixel aperture technique for single-chip 2-D and 3-D imaging. In conventional image sensors, the aperture is located at the camera lens. However, in the proposed image sensor, the aperture is integrated on the CMOS image sensor chip and is formed at a metal layer of the CMOS image sensor (CIS) process. A pixel array of the image sensor is composed of the W, R, B, and PA pixels (W pixel with integrated metal aperture) for extracting color and depth information. While the image of the W pixel becomes blurred with increasing distance from a focused object, the image of the PA pixel maintains the sharpness. Therefore, the depth image can be obtained using the depth from the defocus method. The size of the pixel, which is based on a four-transistor active pixel sensor with pinned photodiode, is $2.8 \,\,\mu {\mathrm{ m}} \times 2.8\,\,\mu \text{m}$ . A prototype of the proposed image sensor was fabricated using the 0.11- $\mu \text{m}$ CIS process and its performance was evaluated.

Development and implementation of novel sensor fusion algorithm for occupancy detection and automation in energy efficient buildings

This paper deals with achieving both energy efficiency and comfortness in a particular room by controlling lighting and cooling appliances of a building by deploying modern sensors like Thermal sensors and Camera for accurate mapping of the environment parameters. The unique part of this paper is that a Sensor Fusion algorithm has been used in different segments of the room which combine the sensory output from the Thermal Sensor and Camera to ensure that the occupancy detection is done accurately with least amount of fluctuations without any delay. The two algorithms, namely, image processing algorithm and sensor signal processing runs in distributed computing environment in two different processors and the outputs of processing algorithms are received in the master controller through IoT cloud platform. The proposed image processing algorithm is effective in detecting both static and dynamic event changes using background subtraction and ROI based segregation models. The system develops the use of this sensor fusion algorithm to provide an intuitive control of the environment and improve the efficiency of the decision making process using National Instruments MyRIO 1800 and cRIO 9082 processors in LabVIEW platform which also reduces the chances or consequences of any fault occurring in the system.

The Design of a Single-Bit CMOS Image Sensor for Iris Recognition Applications.

This paper presents a single-bit CMOS image sensor (CIS) that uses a data processing technique with an edge detection block for simple iris segmentation. In order to recognize the iris image, the image sensor conventionally captures high-resolution image data in digital code, extracts the iris data, and then compares it with a reference image through a recognition algorithm. However, in this case, the frame rate decreases by the time required for digital signal conversion of multi-bit digital data through the analog-to-digital converter (ADC) in the CIS. In order to reduce the overall processing time as well as the power consumption, we propose a data processing technique with an exclusive OR (XOR) logic gate to obtain single-bit and edge detection image data instead of multi-bit image data through the ADC. In addition, we propose a logarithmic counter to efficiently measure single-bit image data that can be applied to the iris recognition algorithm. The effective area of the proposed single-bit image sensor (174 × 144 pixel) is 2.84 mm2 with a 0.18 μm 1-poly 4-metal CMOS image sensor process. The power consumption of the proposed single-bit CIS is 2.8 mW with a 3.3 V of supply voltage and 520 frame/s of the maximum frame rates. The error rate of the ADC is 0.24 least significant bit (LSB) on an 8-bit ADC basis at a 50 MHz sampling frequency.

Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias.

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths.

An asynchronous data-driven readout prototype for CEPC vertex detector

The Circular Electron Positron Collider (CEPC) is proposed as a Higgs boson and/or Z boson factory for high-precision measurements on the Higgs boson. The precision of secondary vertex impact parameter plays an important role in such measurements which typically rely on flavor-tagging. Thus silicon CMOS Pixel Sensors (CPS) are the most promising technology candidate for a CEPC vertex detector, which can most likely feature a high position resolution, a low power consumption and a fast readout simultaneously. For the R&amp;D of the CEPC vertex detector, we have developed a prototype MIC4 in the Towerjazz 180 nm CMOS Image Sensor (CIS) process. We have proposed and implemented a new architecture of asynchronous zero-suppression data-driven readout inside the matrix combined with a binary front-end inside the pixel. The matrix contains 128 rows and 64 columns with a small pixel pitch of 25 [Formula: see text]m. The readout architecture has implemented the traditional OR-gate chain inside a super pixel combined with a priority arbiter tree between the super pixels, only reading out relevant pixels. The MIC4 architecture will be introduced in more detail in this paper. It will be taped out in May and will be characterized when the chip comes back.