Design and Performance of a Pinned Photodiode CMOS Image Sensor Using Reverse Substrate Bias.

Konstantin Stefanov,Andrew Clarke,Andrew Holland,James Ivory

doi:10.3390/s18010118

Konstantin Stefanov, Andrew Clarke + Show 2 more

Open Access

https://doi.org/10.3390/s18010118

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Abstract

A new pinned photodiode (PPD) CMOS image sensor with reverse biased p-type substrate has been developed and characterized. The sensor uses traditional PPDs with one additional deep implantation step to suppress the parasitic reverse currents, and can be fully depleted. The first prototypes have been manufactured on an 18 µm thick, 1000 Ω·cm epitaxial silicon wafers using 180 nm PPD image sensor process. Both front-side illuminated (FSI) and back-side illuminated (BSI) devices were manufactured in collaboration with Teledyne e2v. The characterization results from a number of arrays of 10 µm and 5.4 µm PPD pixels, with different shape, the size and the depth of the new implant are in good agreement with device simulations. The new pixels could be reverse-biased without parasitic leakage currents well beyond full depletion, and demonstrate nearly identical optical response to the reference non-modified pixels. The observed excessive charge sharing in some pixel variants is shown to not be a limiting factor in operation. This development promises to realize monolithic PPD CIS with large depleted thickness and correspondingly high quantum efficiency at near-infrared and soft X-ray wavelengths.

Highlights

Pinned photodiode (PPD) monolithic CMOS image sensors (CIS) are the dominant devices in today’s high performance and consumer imaging due to several key characteristics
The most important part of the sensor characterization was to establish that the DDE cuts off the leakage current under reverse substrate bias as intended
The device uses a new method for leakage current suppression show successful operation

Summary

Introduction

Pinned photodiode (PPD) monolithic CMOS image sensors (CIS) are the dominant devices in today’s high performance and consumer imaging due to several key characteristics. The use of charge transfer between the PPD and the sense node separates the functions of charge collection and charge-to-voltage conversion [1] and allows the sense node to be optimized separately and to be much smaller than the PPD. Optimal correlated double sampling can be implemented for suppression of kTC noise, and together with the very low sense node capacitance makes it possible to routinely achieve sub-electron read noise [2]. The dark current in PPD pixels is very low because of the nearly complete suppression of the surface electron-hole generation by the shallow pinning layer [3], which helps to significantly reduce the image lag [4]. High QE devices are normally back-side illuminated and made on very high resistivity (≈10 kΩ·cm) bulk silicon, their normal operating voltages are not sufficient to achieve full depletion beyond approximately 50 μm

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