III-V Heterojunction Research Articles

Analytical modeling of III-V heterojunction source-all-around vertical tunnel FET and its inverter circuit application

Abstract This paper presents a comprehensive analytical modeling framework for the III-V heterojunction source-all-around vertical tunnel field-effect transistor (SAA V-TFET). Using Kane’s model, our approach involves solving Poisson’s equations to obtain a continuous surface potential profile, followed by the derivation of drain current. These models demonstrate excellent accuracy across all operating regions, precisely predicting the potential profile, output, and transfer characteristics of SAA V-TFETs. We implemented the models in MATLAB and validated them against Sentaurus TCAD simulations. Furthermore, we present a comprehensive performance analysis of SAA V-TFET-based digital inverters.

A comparative study of work function variations in III-V heterojunction and homojunction tunnel field-effect transistors

In this paper, we present a comparative study on the impact of work function variations (WFV) between the III-V heterojunction and homojunction tunnel field-effect transistors (TFETs) vis TCAD simulation. It reveals that, in general, the current variation of both devices decrease as the gate voltage increases, and the threshold voltage variations generally increase with the increase of threshold current. However, in comparison to homojunction TFET, heterojunction TFET exhibits the following two differences. 1) The current fluctuation is stronger near the device's OFF-state and weaker near the ON-state, and thus it has a stronger dependence on bias. 2) Both the threshold voltage fluctuations and its dependence on the threshold current are weaker. On the other hand, with an increase in grain size, both homojunction and heterojunction devices manifest more prominent performance fluctuations. Moreover, the dependence of these fluctuations on grain size is roughly comparable for these two device types. Finally, it is observed that 1) the significant current fluctuation at the OFF-state can be mitigated when the device's OFF-state is designed within a region with weaker gate control, and 2) the current normalized coefficient of variation parameter may be unreliable to assess the fluctuation for the case with a few “abnormal” high current values.

Modeling and design of III-V heterojunction solar cells for enhanced performance

Modeling and design of III-V heterojunction solar cells for enhanced performance

Terahertz Communications: Challenges in the Next Decade

Thanks to the abrupt advances in semiconductor technologies, particularly in terms of the operating frequency, the last decade has seen various efforts and trials in attempts to achieve high-throughput wireless communications at terahertz (THz) frequencies. Through the use of several potential device technologies, not only III-V heterojunction bipolar and high-electron-mobility transistors but also silicon complementary metal-oxide-semiconductors and photonic technologies, high data rates of 100 Gbps or more have been successfully demonstrated. Meanwhile, the next generation of wireless communications systems, so called 6G, is already being discussed in research communities worldwide. A terabit per second peak data rate is envisioned, which essentially requires huge spectral resources. The recent considerable attention to 6G communications is implicitly focused on THz communications but is more than a technical curiosity unlike in the past. In this article, we briefly review the progress of THz communications made in the last decade and discuss some of the most challenging issues that need to be overcome for future wireless systems at THz frequencies, including not only the 6G network but also short-range connectivity and fixed wireless links.

1-D Drift-Diffusion Simulation of Two-Valley Semiconductors and Devices

A two-valley formulation of 1-D drift-diffusion transport is presented that takes the coupling between the valleys into account via a new approximation for the nonlocal electric field. The proposed formulation is suitable for the simulation of III-V heterojunction bipolar transistors as opposed to formulations that employ the single electron gas approximation with a modified velocity-field model, which also causes convergence problems. Based on Boltzmann transport equation simulations, model parameters of the proposed two-valley formulation are given for GaAs, InP, InAs, and GaSb at room temperature. Applications of the new formulation are also demonstrated.

Controlling facets and defects of InP nanostructures in confined epitaxial lateral overgrowth

The selective area growth technique, confined epitaxial lateral overgrowth (CELO), enables the growth of lateral III-V heterojunctions integrated on mismatched substrates. In CELO, effective control of facet shapes, as well as defect-free growths are essential to fabricating high-quality nanostructures with custom geometries. Here, the effects of growth temperature, V/III ratio, template alignments, and substrate orientations on the observed facets and defect densities in CELO grown InP and related materials on InP substrates are investigated. The nanostructure facets and defects are determined using a combination of plan-view and cross-sectional transmission electron microscopy. For homoepitaxial CELO growth on InP (100) substrates, growth temperatures below $575{\phantom{\rule{0.16em}{0ex}}}^{\ensuremath{\circ}}\mathrm{C}$, and high V/III ratios of 450 aid in increasing the surface areas of the {111}B facets, while reducing defect densities. Further, by changing template alignments, the effective areas of overgrowth can be tuned, and defects can be lowered, with templates aligned along $[0\overline{1}0]$ yielding the largest defect-free areas. By aligning templates in the $[\overline{1}10]$ orientation on a (110) InP substrate, near defect-free overgrowth with perfectly flat perpendicular single ($1\overline{1}$ 0) facets can be achieved. This is an essential feature to enable the growth of lateral III-V heterojunctions, as is demonstrated by growing InP/InGaAs CELO heterojunctions with {110} facets.

Analytical modeling and simulation analysis of T-shaped III-V heterojunction vertical T-FET

Abstract In this paper, we have developed a new 2D compact analytical model for surface potential and drain current for III-V group heterojunction of T-shaped Vertical Tunneling FET with inherited properties of dual modulation effect. The device's surface potential is determined from the compact model, which is the most significant consideration for defining device current characteristics. There have been numerous efforts to predict the electrical characteristics of In0.53Ga0.47As as a heterojunction and to discuss the method of device improvement as a function of mole-fraction, gate-drain biasing potential, gate metal work-function. To determine the tunneling width, the dual modulation effect is used to regulate the biasing voltage at both the source and drain junction. A 2-D Poisson equation is solved for the proposed model by using parabolic approximation method with constant electric field which are used to determine the effect of In0.53Ga0.47As as a comparison to Silicon and SiGe material device. Moreover, a new expression of channel surface potential is derived that can forecast the effect of drain and gate biasing. The derived model results validation is carried out by the comparison with the results obtained by TCAD simulation.

A comprehensive analysis of Auger generation impacted planar Tunnel FETs

Tunnel Field Effect Transistors (TFETs) are known to be compromised by higher order processes that downgrade their performance compared to ballistic projections. Using a quasi-analytical model that extends the chemistry based Simmons equation to include finite temperature effects, potential variations and scattering, we exhibit that non-idealities like trap-assisted tunneling and Auger generation can explain the observed performance discrepancy. In particular, Auger generation is the dominant leakage mechanism in TFETs at low trap densities. Our studies suggest that possible ways of reducing Auger generation rate are reducing source carrier concentration and increasing the valence band transport effective mass of the source material. In this paper, we specifically investigate the impact of variations of these factors on device performance of staggered bandgap planar III-V heterojunction Tunnel FETs.

(Invited) Complementary III-V Heterojunction Tunnel FETs Monolithically Integrated on Silicon

Conventional scaling is hampered by the inability to further reduce operating voltages. The main reason for this is the limitation on the subthreshold swing of a MOSFET which determines the abruptness of the on-off transition. This is an inherent limitation of the MOSFET device physics and cannot be remedied by the introduction of novel materials or architectures, but remains an underlying physical limitation. A number of devices have been proposed to overcome this limitation, of those, the most promising in a CMOS setting remains the tunnel FET (TFET). Within the past decade, initial euphoria regarding TFET properties were replaced by more realistic hopes as more thorough simulations brought a deeper understanding of device limitations and opportunities. In this respect it became clear that careful device design and a stringent control of defects is required to realize the promise of TFETs experimentally. Very recently experimental tunnel FETs showing sub-thermionic swing over a significant current range were demonstrated, showing that it is possible to beat CMOS performance. However, technologically heterojunction TFETs are much more complex than a silicon MOSFET. Our focus has been on dense monolithic integration of complementary III-V heterojunction TFETs on silicon, which may eventually evolve into a hybrid technology platform. In this talk we will give a general overview of the development of TFETs, discuss the challenges and opportunities both at the individual device level as well as in terms of technology development.

(Invited) Complementary III-V Heterojunction Tunnel FETs Monolithically Integrated on Silicon

The tunnel FET (TFET) is considered as one of the most promising devices for ultra-low power operation, and it is clear that heterojunction devices are required to achieve simultaneously steep slope and high on-current (Ion). However, technologically, heterojunction TFETs are much more complex than a silicon MOSFET. Our focus has been on dense monolithic integration of complementary III-V heterojunction TFETs on silicon, which may eventually evolve into a hybrid technology platform. In this paper we will give a general overview of the development of TFETs, discuss the challenges and opportunities both at the individual device level as well as in terms of technology development. In particular we will focus on the role of defects on device performance.

Tunnel FETs for ultra low Power Nanoscale Devices

Future ICs are facing dramatic challenges in performance as well as static and dynamic power consumption, which could be overcome using disruptive concepts, device architectures, technologies and materials. Promising solutions includes III-V channels, heterojunctions, 2D layers, multi-gates structures, nanowires (NWs), tunnel FETs (TFETs), ferroelectric FETs (Fe-FETs), and hybrid devices. In the domain of small slope switches, which are very interesting for ultra low power operation, TFETs, Fe-FETs and hybrid devices seem very promising. Thus far, no one has experimentally demonstrated a TFET that has simultaneously both a CMOS-competitive driving current Ion and a sub-60 mV/decade subthreshold swing over several decades. But recently, substantial improvements of TFET and hybrid device performance have been reported, showing that these novel device architectures using new materials and carrier transport could be used for several applications.

Model for transport and reaction of defects and carriers within displacement cascades in gallium arsenide

A model is presented for recombination of charge carriers at evolving displacement damage in gallium arsenide, which includes clustering of the defects in atomic displacement cascades produced by neutron or ion irradiation. The carrier recombination model is based on an atomistic description of capture and emission of carriers by the defects with time evolution resulting from the migration and reaction of the defects. The physics and equations on which the model is based are presented, along with the details of the numerical methods used for their solution. The model uses a continuum description of diffusion, field-drift and reaction of carriers, and defects within a representative spherically symmetric cluster of defects. The initial radial defect profiles within the cluster were determined through pair-correlation-function analysis of the spatial distribution of defects obtained from the binary-collision code MARLOWE, using recoil energies for fission neutrons. Properties of the defects are discussed and values for their parameters are given, many of which were obtained from density functional theory. The model provides a basis for predicting the transient response of III-V heterojunction bipolar transistors to displacement damage from energetic particle irradiation.

Investigation of Backgate-Biasing Effect for Ultrathin-Body III-V Heterojunction Tunnel FET

This paper investigates the impact of backgate biasing (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BS</sub> ) on the drain current (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> ) of ultrathin-body III-V heterojunction tunnel FET (HTFET). Compared with homojunction TFET and III-V/Ge MOSFET, this paper indicates that HTFET exhibits significantly higher I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> (I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> at VGS = 0 V and V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DS</sub> = 0.5 V) modulation efficiency and the influence of V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BS</sub> rapidly decreases with increasing V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">GS</sub> . In addition, it is observed that the change of source available states with V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BS</sub> determines the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> modulation efficiency of p-type HTFET (pHTFET). Depending on the source doping concentration and operating VGS, the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> of HTFET under forward V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BS</sub> can be anomalously smaller than that at V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">BS</sub> = 0 V. Furthermore, the impacts of source/drain doping concentrations and junction properties are discussed and shown to be critical in determining the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">D</sub> modulation efficiency of HTFET. We find that, under controlled ambipolar current, reverse backgate biasing can be utilized to suppress the I <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">OFF</sub> of HTFET, and the modulation efficiency increases with decreasing source doping concentration. Our study may provide insights for device/circuit designs with advanced TFET technologies.

Tunnel FET RF Rectifier Design for Energy Harvesting Applications

Radio-frequency (RF)-powered energy harvesting systems have offered new perspectives in various scientific and clinical applications such as health monitoring, bio-signal acquisition, and battery-less data-transceivers. In such applications, an RF rectifier with high sensitivity, high power conversion efficiency (PCE) is critical to enable the utilization of the ambient RF signal power. In this paper, we explore the high PCE advantage of the steep-slope III-V heterojunction tunnel field-effect transistor (HTFET) RF rectifiers over the Si FinFET baseline design for RF-powered battery-less systems. We investigate the device characteristics of HTFETs to improve the sensitivity and PCE of the RF rectifiers. Different topologies including the two-transistor (2-T) and four-transistor (4-T) complementary-HTFET designs, and the n-type HTFET-only designs are evaluated with design parameter optimizations to achieve high PCE and high sensitivity. The performance evaluation of the optimized 4-T cross-coupled HTFET rectifier has shown an over 50% PCE with an RF input power ranging from -40 dBm to -25 dBm, which significantly extends the RF input power range compared to the baseline Si FinFET design. A maximum PCE of 84% and 85% has been achieved in the proposed 4-T N-HTFET-only rectifier at -33.7 dBm input power and the 4-T cross-coupled HTFET rectifier at -34.5 dBm input power, respectively. The capability of obtaining a high PCE at a low RF input power range reveals the superiority of the HTFET RF rectifiers for battery-less energy harvesting applications.

A Steep-Slope Tunnel FET Based SAR Analog-to-Digital Converter

This paper explores the energy efficiency advantage of a 6-bit III-V heterojunction tunnel field-effect transistor (HTFET) based successive-approximation register (SAR) analog- to-digital converter (ADC) with 20-nm gate length. Compared with the Silicon FinFET (Si FinFET) ADC, the HTFET SAR ADC achieves approximately 3 times power consumption reduction and 6 times size reduction. Signal-to-noise and distortion ratio is 31. 4d B for the HTFET SAR ADC, which is 2.81 dB higher than the Si FinFET ADC due to the decreased quantization noise rising from the high ON-current characteristic of HTFET at low supply voltage. The energy per conversion step for both HTFET and Si FinFET ADC designs are 0.43 and 1.65 fJ/conversion-step, respectively, at a fixed supply voltage of 0.30 V. Index Terms—Analog-to-digital converter (ADC), heterojunc- tion tunnel FET (HTFET), successive-approximation register (SAR), ultra-low-power.

Soft-Error Performance Evaluation on Emerging Low Power Devices

Radiation-induced single-event upset (SEU) has become a key challenge for cloud computing. The proposed introduction of low bandgap materials (Ge, III-Vs) as channel replacement and steep switching devices for low-voltage applications may induce radiation reliability issues due to their low ionization energy and device architecture. In this paper, the soft-error generation and propagation in Si FinFET, III-V FinFET, and III-V Hetero-junction tunnel FET (HTFET) are investigated using device and circuit simulation. III-V FinFET shows enhanced charge collection compared with Si FinFET, whereas HTFET shows significant reduction of the bipolar gain effect and charge collection. Soft-error rate (SER) evaluation methodology has been proposed for these emerging devices based on the critical LET extraction. SRAM bit flip, electrical masking effect, and latching window masking effect have been analyzed with supply voltage scaling. The SER evaluation of SRAM and logic shows that HTFET-based circuits are promising for radiation resilient ultra-low power applications. III-V FinFET shows increased SER for SRAM for ${\rm V}_{\rm DD}$ range of 0.3–0.8 Vand reduced logic SER below 0.5 V compared with Si FinFET.

Impact of Single Trap Random Telegraph Noise on Heterojunction TFET SRAM Stability

We investigate the effect of a single charge trap random telegraph noise (RTN)-induced degradation in III-V heterojunction tunnel FET (HTFET)-based SRAM. Our analysis focuses on Schmitt trigger (ST) mechanism-based variation tolerant ten-transistor SRAM. We compare iso-area SRAM cell configurations in Si-FinFET and HTFET. Our results show that HTFET ST SRAMs provide significant energy/performance enhancements even in the presence of RTN. For sub-0.2 V operation (Vcc), HTFET ST SRAM offers 15% improvement in read-write noise margins along with better variation immunity from RTN over Si-FinFET ST SRAM. A comparison with iso-area 6T Si-FinFET SRAM with wider size transistors shows 43% improved read noise margin in 10T HTFET ST SRAM at Vcc=0.175 V. In addition, HTFET ST SRAM exhibits 48X lower read access delay and 1.5X reduced power consumption over Si-FinFET ST SRAM operating at their respective Vcc-min.

Electrical Noise in Heterojunction Interband Tunnel FETs

We present an analysis of electrical noise in III-V heterojunction TFET (HTFET). Using numerical simulations, random telegraph noise (RTN) amplitude induced by a single charge trap is investigated with regard to trap location, electron band-to-band-generation rate, bias, and transistor size. It is found that HTFET RTN amplitude does not scale inversely with gate length and is governed by tunneling distance of carriers at source-channel junction. HTFET exhibits 40% less relative RTN amplitude at 0.3 V at gate lengths around 20 nm, over subthreshold Si-FinFET. RTN of HTFET at VGS=0 V is higher for a trap location at source-channel tunnel junction. To analyze flicker, shot, and thermal noise, we created transistor level Verilog-A-based electrical noise models. The results indicate HTFETs competitive noise performance in megahertz frequency range, over Si-FinFET. In the range 10 GHz or more with operating voltages exceeding 0.3 V, HTFET input noise is worse due to the dominance of shot noise. A differential amplifier with active load is used to examine the electrical noise performance at circuit level. We emphasize that high intrinsic gain, drive current, and output resistance of HTFET can be used to achieve superior mixed signal performance metrics in HTFET design over Si-FinFET design, at an improved electrical noise performance.

Radiation Effects in SiGe Technology

Silicon-Germanium (SiGe) technology effectively merges the desirable attributes of conventional silicon-based CMOS manufacturing (high integration levels, at high yield and low cost) with the extreme levels of transistor performance attainable in classical III-V heterojunction bipolar transistors (HBTs). SiGe technology joins together on-die high-speed bandgap-engineered SiGe HBTs with conventional Si CMOS to form SiGe BiCMOS technology, including all the requisite RF passive elements and multi-level thick-Al metalization required for high-speed circuit design. Such an silicon-based integrated circuit technology platform presents designers with an ideal division of labor for realizing optimal solutions to many performance-constrained mixed-signal (analog + digital + RF) systems. The unique bandgap-engineered features of SiGe HBTs enable several key merits with respect to operation across a wide variety of so-called “extreme environments”, potentially with little or no process modification, ultimately providing compelling advantages at the circuit and system level, across a wide class of envisioned commercial and defense applications. Here we give an overview of this interesting field, focusing primarily on the intersection of SiGe HBTs, and circuits built from them, with radiation-intense environments such as space.

Spin-orbit interaction strength and anisotropy in III-V semiconductor heterojunctions

The spin-orbit interaction strength for electrons in III-V semiconductor heterojunctions and the corresponding in-plane anisotropy are theoretically studied, considering Rashba and Dresselhaus contributions. Starting from a variational solution of Kane's effective Hamiltonian for the Rashba-split subbands, the total spin-orbit splitting at the Fermi level of the two-dimensional electron gas in III-V heterojunctions is calculated analytically, as a function of the electron density and wave-vector direction, by adding the Dresselhaus contribution within quasidegenerate first-order perturbation theory. Available GaAs and InGaAs experimental data are discussed. Effects of the barrier penetration are identified, and the spin-orbit anisotropy is shown to be determined by more than one parameter, even in the small-$k$ limit, contrary to the commonly used $\ensuremath{\alpha}/\ensuremath{\beta}$ (where $\ensuremath{\alpha}$ is the Rashba and $\ensuremath{\beta}$ the Dresselhaus interaction) single-parameter picture.