Tunnel FETs for ultra low Power Nanoscale Devices

Abstract

Future ICs are facing dramatic challenges in performance as well as static and dynamic power consumption, which could be overcome using disruptive concepts, device architectures, technologies and materials. Promising solutions includes III-V channels, heterojunctions, 2D layers, multi-gates structures, nanowires (NWs), tunnel FETs (TFETs), ferroelectric FETs (Fe-FETs), and hybrid devices. In the domain of small slope switches, which are very interesting for ultra low power operation, TFETs, Fe-FETs and hybrid devices seem very promising. Thus far, no one has experimentally demonstrated a TFET that has simultaneously both a CMOS-competitive driving current Ion and a sub-60 mV/decade subthreshold swing over several decades. But recently, substantial improvements of TFET and hybrid device performance have been reported, showing that these novel device architectures using new materials and carrier transport could be used for several applications.