Effects of Forming Gas Annealing and Channel Dimensions on the Electrical Characteristics of FeFETs and CMOS Inverter

Po-Jung Sung,Shih-Hsuan Lo,Darsen D Lu,Yao-Jen Lee,Tien-Sheng Chao,Chun-Jung Su,Fu-Kuo Hsueh

doi:10.1109/jeds.2020.2987005

Abstract

In this study, ferroelectric FETs (FeFETs) and CMOS inverters are fabricated and analyzed, exhibiting 13% of 593 devices with sub-60 mV subthreshold swing (SS) at room temperature. Forming gas annealing (FGA) is found to not only enhance ferroelectricity but also significantly improve FeFET electrostatics. The experimental results indicate that FeFET with a narrow width shows weaker ferroelectric properties, and SS of sub-60 mV/dec with ID change less than two orders of magnitude. However, FeFET with a broad channel width reveals stronger ferroelectric properties, and SS of sub-60 mV/dec is over 2 orders of magnitude of Id. Finally, typical voltage transfer characteristics (VTCs) of a FeFET CMOS inverter with double sweeps at various VD from 0.6 to 2 V are demonstrated. The results show that hysteresis in a FeFET CMOS inverter could have both clockwise (CW) and counter-clockwise (CCW) loops.

Highlights

Low power devices with very low supply voltage are attractive for emerging applications, such as high-end computational units or battery-powered portable electronics
For P-V measurement, the samples were fabricated as the same gate stack process on highly doped n-type silicon to form ferroelectric MIS structures (TiN/HfZrO2/SiO2/N+)
ferroelectric FETs (FeFETs) with wide and narrow widths are fabricated on the same SOI wafer for this study

Summary

INTRODUCTION

Low power devices with very low supply voltage are attractive for emerging applications, such as high-end computational units or battery-powered portable electronics. Unlike conventional planar MOSFETs, 3D FinFET has a fabrication issue about fin sidewall roughness. FinFET with a narrow channel width has a serious fin sidewall roughness issue and a higher density of traps (Dit) [9], which could deteriorate SS of ferroelectric FinFET. SUNG et al.: EFFECTS OF FORMING GAS ANNEALING AND CHANNEL DIMENSIONS ON ELECTRICAL CHARACTERISTICS is over two orders of magnitude of ID [10]–[14]. The forming gas annealing process has been proved effective in improving the surface roughness of Si-fin in CMOS FinFETs [19]–[21]. We use forming gas annealing on the gate stack of FeFET to improve device performance and analyze electrical characteristics further, such as polarization, capacitance, SS, and hysteresis. We fabricate a FeFET CMOS inverter experimentally and analyze the effect of hysteresis on VTCs of a CMOS inverter

DEVICE FABRICATION

RESULTS AND DISCUSSIONS

CONCLUSION