(Invited) Complementary III-V Heterojunction Tunnel FETs Monolithically Integrated on Silicon

Abstract

Conventional scaling is hampered by the inability to further reduce operating voltages. The main reason for this is the limitation on the subthreshold swing of a MOSFET which determines the abruptness of the on-off transition. This is an inherent limitation of the MOSFET device physics and cannot be remedied by the introduction of novel materials or architectures, but remains an underlying physical limitation. A number of devices have been proposed to overcome this limitation, of those, the most promising in a CMOS setting remains the tunnel FET (TFET). Within the past decade, initial euphoria regarding TFET properties were replaced by more realistic hopes as more thorough simulations brought a deeper understanding of device limitations and opportunities. In this respect it became clear that careful device design and a stringent control of defects is required to realize the promise of TFETs experimentally. Very recently experimental tunnel FETs showing sub-thermionic swing over a significant current range were demonstrated, showing that it is possible to beat CMOS performance. However, technologically heterojunction TFETs are much more complex than a silicon MOSFET. Our focus has been on dense monolithic integration of complementary III-V heterojunction TFETs on silicon, which may eventually evolve into a hybrid technology platform. In this talk we will give a general overview of the development of TFETs, discuss the challenges and opportunities both at the individual device level as well as in terms of technology development.