III-V Channel Research Articles

Monte Carlo simulations of spin transport in nanoscale transistors: temperature and size effects

Spin-based metal-oxide-semiconductor field-effect transistors (MOSFETs) with a high-mobility III-V channel are studied using self-consistent quantum corrected ensemble Monte Carlo device simulations of charge and spin transport. The simulations including spin–orbit coupling mechanisms (Dresselhaus and Rashba coupling) examine the electron spin transport in the 25 nm gate length MOSFET. The transistor lateral dimensions (the gate length, the source-to-gate, and the gate-to-drain spacers) are increased to investigate the spin-dependent drain current modulation induced by the gate from room temperature of 300 K down to 77 K. This modulation increases with increasing temperature due to increased Rashba coupling. Finally, an increase of up to 20 nm in the gate length, source-to-gate, or the gate-to-drain spacers increases the spin polarization and enhances the spin-dependent drain current modulation at the drain due to polarization-refocusing effects.

Improvement in the Performance of III-V Channel Based Ultra-Thin Junction-Less-Hybrid CMOS Circuits with Mixed Mode Analysis

The logic performance of a hybrid complementary-metal-oxide-semiconductor (CMOS) circuit based on a novel technology known as a junctionless transistor constructed with high-K and III-V compound material Junction-Less-Double-Gate MOSFET (JL-DG-MOSFET) for ultra-low power applications is analyzed in this manuscript. The mentioned CMOS circuit is constructed by using a Ge-based P-MOS and GaAs-based N-MOS to analyze different performance metrics of inverter such as noise margin (NM), voltage transfer characteristics, transient response, gain, frequency response, and propagation delay using Mixed Mode Analysis. The aforementioned characteristics of the proposed inverter are analyzed and compared with the Si-based CMOS inverter and we observed that the proposed structure shows an improved circuit performance over the Si-based CMOS circuit. Consequently, the work is also extended to the design and performance of universal logic gates. The aforementioned N-MOS structure has a higher drive current of 1.3 mA, gm of 5.9 mS, gd of 20.8 mS, SS of 64 mV Decade−1, and DIBL of 23 mV V−1, whereas the Ge based P-MOS structure yields drive current of 0.7 mA, gm of 1.5 mS, gd of 5.6 mS, SS of 95 mV Decade−1, and DIBL of 21 mV V−1. The hybrid C-MOS structure has higher unity-gain bandwidth of 1100 GHz and lower propagation delay of 3.1 ps, as well as static and dynamic power dissipation of 1.86 nw and 0.23 mw.

Mitigating DIBL and Short-Channel Effects for III-V FinFETs With Negative-Capacitance Effects

This paper, based on the IRDS 2022 technology node, investigates the DIBL and short-channel effects for InGaAs negative-capacitance FinFETs (NC-FinFETs) through a theoretical subthreshold drain current model considering key effects including negative capacitance, quantum confinement and source-to-drain tunneling. Due to the impact of negative capacitance on the source-to-drain potential profile, tunneling distance and its drain-bias dependence, the short-channel effects can be substantially improved for InGaAs NC-FinFETs. Our study indicates that, with the larger NC effect of the III-V channel, the gap in DIBL and subthreshold swing between InGaAs and Si FinFETs in the sub-20 nm gate-length regime can become much closer. Our study may provide insights for future supply-voltage/power scaling of logic devices with high-mobility channel.

Physics based compact modeling of symmetric double gate MOS transistors with high mobility III-V channel material

In this work, we report a physics-based core model of surface potential, inversion charge, and drain current of a symmetric double-gate MOSFET with high mobility III-V channel material. The model efficiently captures all essential device physics of III-V MOSFETs. The carrier quantization effect inside the quantum well formed between oxide and channel region, is modeled by solving time-independent Schrödinger wave equation. The surface potential and inversion charge are obtained from the explicit solution of the Poisson and Schrödinger equation. A first-order correction has been applied to incorporate the modifications in sub-band energy due to applied gate bias voltages. The conduction band non-parabolicity effect is also included in our proposed model. The drain current has been derived using drift-diffusion transport including the velocity overshoot effect. The core model is free from any empirical parameters. The model predicted results have been validated with self-consistent Schrödinger-Poisson solver and commercial device simulator (TCAD) for different channel thicknesses, effective masses, a wide range of gate and drain bias voltages, and different non-parabolicity factor. The model predicted results are found to be in reasonable agreement with numerical simulation data.

Center Potential Based Analysis of Si and III-V Gate all around Field Effect Transistors (GAA-FETs)

In this brief, the center potential based analysis of Si and AlGaN/GaN gate all around field effect transistors (GAA-FET) is presented. The center potential is calculated for different values of channel length, channel height, doping concentration, and thickness of oxide layer using numerical simulations and analytical modeling. The results obtained using numerical simulations through TCAD are validated and found in decent accord with the analytical modeling. The lower effective mass of the III-V channel material results in the lower density of states (DOS), so quantum capacitance reduces significantly in III-V GAA-FET as compared to Si. This small DOS of III-V directly results in a low sheet carrier concentration at a certain gate overdrive voltage for III-V GAA-FET. The analog and linearity/distortion parameters of III-V and Si GAA-FET are calculated and compared. The utility of the III-V GAA-FET extends in high speed and low power digital logic applications, RF design applications including low noise and very high frequency due to better electron transport properties than Si.

Investigation of Inversion Charge Characteristics and Inversion Charge Loss for InGaAs Negative-Capacitance Double-Gate FinFETs Considering Quantum Capacitance

This paper investigates the inversion charge characteristics and quantum-capacitance induced inversion charge loss for In 0.53 Ga 0.47 As negative-capacitance FinFETs (NC-FinFETs) using theoretical calculation corroborated with numerical simulation. Our study indicates that, the boost of inversion charges due to negative capacitance increases with increasing remnant polarization Pr. In addition, the inversion charge boosting for the In 0.53 Ga 0.47 As device is significantly larger than that of the Si (110) device due to the step-like inversion capacitance characteristic stemming from the 2D density-of-states of the In 0.53 Ga 0.47 As device. In other words, the quantum-capacitance induced inversion-charge loss for III-V channel can be mitigated in NCFETs.

(Invited) Vertical Tunnel FET Technologies Using III-V/Si Heterojunction

Conventional field-effect transistors (FETs) have inherent issues for lowering supply voltage because there is physical limitation of subthreshold slope (SS = 2.3 k BT/q = 60 mV/dec), which determine supply voltage of FETs. This limitation will stop further scaling of the power consumption even if a multi-gate architecture and III-V/Ge channels are implemented. Thus, non-thermionic switches achieving steep SS have attracted much attentions as a building blocks for future low-power integrated circuits. Among the switches, tunneling FET (TFETs) are promising alternative FETs because their good Si-CMOS compatibility and very small off-state leakage current due to band offset across the tunnel junction. There are, however, still challenges in achieving steep SS with wide range of current, high conductance, and complementary operation. In this talk we reported on recent technologies for vertical TFET using III-V/Si tunnel junctions [1,2], which is formed by selective-area growth of III-V nanowires (NWs) on Si [3-5], and demonstrated vertical TFETs with steeper SS below physical limitation. Next, we investigate current-boosting technologies by using core-shell structure induced strain and modulation-doping of the NW-channels. Moreover, we demonstrate complementary switching operation with very steep SS and very high transconductance efficiency by using same device architecture. This new tunnel junctions can inherently forms abrupt heterojunction regardless of precise doping because the band discontinuity is determined only by the offset of each III-V and Si. Thus, good gate-electrostatic control and depletion-width control for the tunnel transport is defined only by the III-V channel region regardless of degeneration of source materials. As for integration of III-V NWs on Si, selective-area growth has no thick buffer layer, thus the III-V NWs/Si interface is able to show unique band structures. The narrow gap III-Vs such as In0.7Ga0.3As NWs, for instance, exhibits staggered-Type II band structure when the n-type NWs are formed on p-Si substrates regardless precise doping. Thus, we integrated the InGaAs NWs on Si substrate by utilizing specific growth sequence to align vertical NWs [6]. Sn was used for n-type dopant, and Zn-pulse doping technique [7] was used to make pseudo intrinsic layer as channel region. The formation of intrinsic layer in such small NW-volume would be very important to induce large internal electrical field at the InGaAs/Si heterojunction. The length of the Zn-pulse doped region correspond to channel-length (200 nm-long in this case). AS for high-performance TFETs, we demonstrated a high-performance switch using a vertical nanowire-channel consisting of InGaAs/Si tunnel junction with two-dimensional electron gas. The device exhibit rapid enhancement in conductance with steep slope over four magnitude of decades, and complementary switching operation by inverting the ground terminal (minimum slope of 25 mV/decade as n-channel, or 6 mV/decade as p-channel at 0.25 V). Furthermore, the transconductance efficiency, meaning the current efficiency of integrated circuits, exceeds the theoretical limit in conventional circuits which was around 1900 /V (physical limitation of conventional MOSFET is 38.5 /V).

(Invited) Wet-Chemical Etching of III-V Semiconductors: Towards Atomic-Layer-Scale Processing

Recent developments in device technology resulted in an upsurge of interest in III-V compound semiconductors. These include improved fabrication techniques for flexible electronic devices,[1,2] and epitaxial integration of various III-V channel materials on Si-based platform wafers enabling the development of highly scaled CMOS transistors [3–5] and nanophotonic devices [6]. While fabrication strategies for traditional III-V optoelectronic devices such as light-emitting diodes, lasers and solar cells are well established, the very small dimensions of these new nanodevices pose new problems. In such applications wet-chemical etching remains an essential step. The ever decreasing size of III-V devices requires ultimately atomic-layer-scale control of surfaces in terms of etching selectivity, stoichiometry and morphology.[7,8] Considerable expertise and literature is currently available on III-V semiconductor etching[9,10]. However, much of the reported work is empirical, etch rates are high, and mechanistic insight into (electro)chemical processes occurring at the semiconductor-solution interface is often lacking. In this work an overview will be given of wet-chemical approaches for nanoscale and atomic-layer-scale etching of Ga(In)As and InP. Two types of etching systems will be discussed. The first is based on the use of acidic H2O2 solution. Inductively coupled plasma mass spectrometry (ICP-MS) measurements, used to determine etching kinetics, showed that under similar conditions the etch rate of Ga(In)As in H2SO4/H2O2 solution is more than an order of magnitude higher than that of InP. Another striking observation is the influence of the acid, H2SO4 and HCl, on etching kinetics. An increase in HCl concentration leads to an increase in the etch rate of InP while the dissolution rate of Ga(In)As is markedly lowered for the active etching range. Previous work suggested that the surface oxide or hydroxide may be important.[11,12] We have used X-ray photoemission spectroscopy (XPS) and time-of-flight elastic recoil detection analysis (ToF-ERDA) to obtain information about (hydr)oxide formation on the etched surfaces. ToF-ERDA measurements also allowed us the detect surface chlorine in the case of HCl-based etchants. The results indicate that, while the initial step (the breaking of the III-V surface bond) is the same for both semiconductors, the ease with which the resulting group V hydroxide entity at the surface can be deprotonated determines whether the etch rate will be high (Ga(In)As) or low (InP). The mechanism can also help to explain the contrasting role of HCl in the dissolution of the two semiconductors. An alternative digital type of etching approach for InGaAs and InAs involves self-limiting surface oxidation in O3/H2O followed by an oxide removal step in HCl solution[12]. ICP-MS quantification of the dissolved surface oxide species indicates that a high stoichiometry of etching is obtained and that the number of equivalent oxidized atomic layers can be controlled by adjusting the dissolved O3 concentration. For >4 cycles some surface roughening is observed, most likely due to due to the high solubility of As oxides in water. An important advantage of the 2-step approach is that defect selective etching can be effectively suppressed. Examples of applications of the two etching systems will be highlighted. [1] C.-W. Cheng, K.-T. Shiu, N. Li, S.-J. Han, L. Shi, D.K. Sadana, Nat. Commun. 4 (2013) 1577. doi:10.1038/ncomms2583[2] N.J. Smeenk, J. Engel, P. Mulder, G.J. Bauhuis, G. Bissels, J.J. Schermer, E. Vlieg, J.J. Kelly, ECS J. Solid State Sci. Technol. 2 (2013) P58–P65.[3] J.A. del Alamo, Nature. 479 (2011) 317–323. doi:10.1038/nature10677[4] M. Paladugu, C. Merckling, R. Loo, O. Richard, H. Bender, J. Dekoster, W. Vandervorst, M. Caymax, M. Heyns, Cryst. Growth Des. 12 (2012) 4696–4702. doi:10.1021/cg300779v[5] N. Waldron, C. Merckling, L. Teugels, P. Ong, S.A.U. Ibrahim, F. Sebaai, A. Pourghaderi, K. Barla, N. Collaert, A.V.-Y. Thean, IEEE Electron Device Lett. 35 (2014) 1097–1099. doi:10.1109/LED.2014.2359579[6] Y. Shi, Z. Wang, J. Van Campenhout, M. Pantouvaki, W. Guo, B. Kunert, and D. Van Thourhout, Optica 4, 1468-1473 (2017). doi:10.1364/OPTICA.4.001468[7] K.J. Kanarik, T. Lill, E.A. Hudson, S. Sriraman, S. Tan, J. Marks, V. Vahedi, R.A. Gottscho, J. Vac. Sci. Technol. Vac. Surf. Films. 33 (2015) 020802. doi:10.1116/1.4913379[8] G.S. Oehrlein, D. Metzler, C. Li, ECS J. Solid State Sci. Technol. 4 (2015) N5041–N5053. doi:10.1149/2.0061506jss[9] P.H.L. Notten, J.E.A.M. Meerakker, J.J. Kelly, Elsevier Advanced Technology, 199.[10] A.R. Clawson, Mater. Sci. Eng. R Rep. 31 (2001) 1–438[11] D.H. van Dorp, S. Arnauts, D. Cuypers, J. Rip, F. Holsteyns, S.D. Gendt, J.J. Kelly, ECS J. Solid State Sci. Technol. 3 (2014) P179–P184. doi:10.1149/2.021405jss[12] D.H. van Dorp, S. Arnauts, F. Holsteyns, S.D. Gendt, ECS J. Solid State Sci. Technol. 4 (2015) N5061–N5066. doi:10.1149/2.0081506jss

2D and 3D TCAD simulation of III-V channel FETs at the end of scaling

Quantum drift diffusion corrections, models for the one- and two-dimensional density of states, a non-local model for source-to-drain tunneling, and a simple ballistic mobility model are jointly used to simulate IDVGS-characteristics of scaled III-V-channel nFETs. The sub-threshold swing of double-gate ultra-thin-body and gate-all-around nanowire geometries are extracted for different gate lengths, and the semi-classical results are compared with those from the quantum transport simulator QTx. The low-dimensional density of states in combination with the ballistic mobility yields an overall good agreement with the QTx transfer curves after the onset of inversion and decreases ION by two orders of magnitude in comparison to the simulation with a large diffusive mobility. It is shown that source-to-drain tunneling sets a limit to scaling at a gate length of about 10nm due to the degradation of the sub-threshold swing. Simulating this effect with a low-dimensional density of states reveals inconsistencies. They are attributed to the tunneling model, which had been derived for a three-dimensional electron gas.

Effect of Low Temperature RF Plasma Treatment on Electrical Properties of Junctionless InGaAs MOSFETs

In this paper, we study the effect of low-temperature RF plasma treatment in forming gas (10%H2+90%N2) on the electrical characteristics of junctionless MOSFETs with n-In0.53Ga0.47As channel and an Al2O3 gate dielectric. The impact of plasma power density on the device parameters is investigated. It is found that RF plasma annealing with a low power density (0.5 W/cm2) at 150°C for 10 min provides substantial improvement of source/drain contacts resistance and the carrier mobility resulting in a considerable increase of the on-state current and transconductance. It also improves the subthreshold slope and reduces the fixed positive charge in Al2O3 under the gate, shifting the threshold voltage toward positive values. It is demonstrated that non-thermal factors play a principle role in modification of electrical properties of the JL MOSFETs under RF plasma treatment. Such treatment may be an efficient tool for the improvement of the performance of the advanced MOSFETs with III-V channel materials.

Geometric structure and electronic properties of wurtzite GaN/HfO2 interface: A first-principles study

III-V interface with high-k oxide, especially HfO2, is crucial to the development of high mobility microelectronic devices. In this work, we systematically investigated the wurtzite GaN/cubic HfO2 interface based on the first-principles calculations with density functional theory in terms of the geometric structure and electronic properties. In order to mimic the high-k growth conditions, the interfacial oxygen contents in the slab interface models varied to study the interface stability and the relevant electronic structures. It is found that the oxygen rich interface, i.e., oxygen content of 83.3% (O5), shows the most stability in a large range of the oxygen chemical potential from 0 eV to −4.34 eV. Through the calculations of local density of states and Bader charge analysis, we noticed that increasing the interfacial oxygen content leads to the increase of the valence band offset (VBO) and the decrease of the conduction band offset (CBO), respectively. More importantly, interface O5 displays a promising VBO (0.86 eV) and CBO (1.34 eV), which meets the industrial requirements to confine the carrier in the III-V channel materials. Furthermore, no interfacial gap states are observed in interface O5, indicating that O5 is free of Fermi level pinning. This theoretical exploration suggests that varying oxygen content at the interface could result in the optimal interface for the applications of high mobility electronic devices.

(Invited) Investigating the Electronic Properties of Narrow Band Gap III-V Mos Systems

The electronic properties of the III-V/oxide MOS system play a central role in applications of compound semiconductors in RF, sensor and photonics based applications. The technique commonly used to probe the electronic properties of oxide/semiconductor interfaces in MOS structures is impedance spectroscopy, where the capacitance and conductance of the MOS system is measured as a function of bias, frequency and temperature [1, 2]. There is a growing interest in the integration of RF/mm wave [3] and photonic [4] components onto a large area silicon platform, to save on the overall use of III-V materials and also to allow more compact system integration. Considering the case of RF and mm wave devices in a MOSFET implementation, there is a need to understand and control electrically active defects at the interface between the III-V channel and the insulating gate oxide. In recent years there has been considerable progress in reducing the interface state density (Dit) [5-8], in narrow gap InGaAs and InGaSb [9] MOS structures to the point where genuine surface inversion can be observed for both n- and p-type InGaAs [8,9]. The research focus for III-V MOS systems is now turning to the issue of defects states in the oxide (border traps) which can communicate with the conduction and valence bands by elastic or inelastic tunnelling [10]. Analysis of these border traps to date has been based on a distributed capacitor/resistor model [10, 11]. In this presentation, we extend these studies by simulating the AC response of border traps (BTs) and interface states by employing a simulator [12, 13] that solves the Poisson, drift-diffusion and charge conservation equations, taking into account the elastic band-to-trap tunneling model [14] for BTs, yielding estimates for the trap volume as well as variation in border trap density with energy and depth into the oxide. The presentation will also provide an overview of the relationship between specific functions of the capacitance (C) conductance (G) for the case of narrow band gap III-V MOS structures which exhibit genuine surface inversion, where the capacitance and conductance of the MOS system as a function of ac angular frequency (ω) are related, and in particular the peak values of G/ω and −dC/dloge(ω) (≡− ωdC/dω) are equal, and that these equal peak magnitudes occur at the same value of ω [15]. The relationship is also confirmed by physics based ac simulations of MOS structures and through analysis of the equivalent circuit model in inversion. Results will be presented for InGaAs and InGaSb MOS structures (Al2O3 and Al2O3/HfO2 ALD oxides) where genuine inversion of the III-V/oxide surface is confirmed by the G/ω and −dC/dloge(ω) functions, which have peak values of Cox 2/2(Cox+Cd) when the surface is inverted (where Cox is the gate oxide capacitance and Cd is the maximum capacitance of the semiconductor surface in inversion). Extending on previous studies [15], this presentation will presents experimental and physics based simulations which indicate the relationship between G/ω and −dC/dloge(ω) holds true in all bias regions of the MOS response. Finally, it is noted that the relation between G/ω and −dC/dloge(ω) is not specific to III-V MOS systems, and is generally true for all MOS systems, and examples will be provides for MOS structures based on a 2 D dimensional semiconductor. All authors acknowledge the financial support of the EU through the INSIGHT project (688784). The authors from Tyndall acknowledge Science Foundation Ireland (15/IA/3131). [1] E. H. Nicollian and J. R. Brews, MOS Physics and Technology. Wiley, 1982 [2] E. H. Nicollian and A. Goetzberger, Bell Syst. Tech. J., 46, 6, pp. 1055–1133, 1967. [3] C. Zota, et. al., IEEE Electron Dev. Lett. vol 37, p1264 (2016) [4] S. Chen, et al., Optics Express Vol. 25, Issue 5, pp. 4632-4639 (2017) [5] É. O’Connor et al., J. Appl. Phys., vol. 109, no. 2, p. 024101, 2011. [6] H.-D. Trinh et al., Appl. Phys. Lett., vol. 97, no. 4, pp. 042903-1–042903-3, 2010. [7] T. D. Lin et al., Appl. Phys. Lett., vol. 100, no. 17, p. 172110, 2012. [8] E. O'Connor, et al. Appl. Phys. Lett 110, 032902 (2017) [9] D. Millar et al., Applied Materials & Interfaces (submitted) [10] Y. Yuan et al., IEEE EDL, 32, 485 (2011) [11] G. Sereni et al., IEEE TED 62, 705, (2015) [12] Synposys Inc., Sentaurus Device TM, v. L-2016.03-SP2 [13] S.E. Laux, IEEE Trans. on Computer-Aided Design of Integrated Circuits and Systems, 4, 478 (1985) [14] F. Jiménez-Molinos et al., JAP, 91 (2002), 5116 [15] Scott Monaghan et al., IEEE Transaction on Electron Devices, 61, 4176 (2014)

(Invited) Ultra-Low Power III-V-Based Mosfets and Tunneling FETs

CMOS and tunneling FETs (TFETs) utilizing low effective mass III-V channels on Si substrates is expected to be one of the promising device options for low power integrated systems, because of the enhanced carrier transport and tunneling properties. In this paper, we present viable device and process technologies of III-V MOSFETs and TFETs on the Si CMOS platform. Heterogeneous integration to form these new materials on Si is a common key issue. The wafer bonding technologies are utilized for this purpose. We demonstrate the operation and the electrical characteristics of a variety of III-V MOSFETs and TFETs including the hetero-structures. One strategy to reduce Vdd is to increase Ion of MOSFETs by employing low effective mass (high velocity) channels. From this viewpoint, III-V/Ge materials are promising. One of the most critical problems for III-V MOSFETs on Si platform is high quality III-V channel formation on Si substrates. As a technology of the III-V channel formation, we are focusing on III-V wafer bonding to Si substrates. We have developed a bonding technology extendable to 300-mm Si wafers, where III-V channels are grown on Si with thick buffers and transferred to Si wafers [1]. The high channel quality with a low defect density has been confirmed from the tight leakage current distribution. By using InGaAs-OI substrates fabricated by wafer bonding, we have demonstrated tri-gate In0.3Ga0.7As (3nm)/InAs (3nm)/In0.3Ga0.7As (3nm)-on-insulator quantum well (QW) MOSFETs [2]. High Ion and suppressed short channel effects have been obtained by the narrow width tri-gate structure and the optimized ultrathin quantum-well channels [2, 3]. Also, the other strategy to reduce Vdd is to realize steep slope devices with low sub-threshold swing (S.S.). Here, TFETs are one of the most promising steep slope devices, which have been regarded as mandatory for future scaled LSIs for ultra-low power and IoT applications [4]. There can be two critical issues to realize high performance TFETs. One issue is the choice of the source/channel materials enabling to increase tunneling current. Thus, semiconductors such as Ge and III-V are expected as suitable materials with small and/or direct band gap for enhancing Ion of TFETs. In addition, source/channel junctions composed of type-II hetero-structures are effective in boosting the TFET performance without increase in the junction leakage current. Also, the second critical issue is the defect-less source tunnel junction formation with the optimum source concentration and the steep source impurity profile, which leads to sufficiently thin tunneling width and resulting high tunneling current with minimized leakage currents. From this viewpoint, the technologies to form the source tunnel junctions are of paramount importance. The source regions of n-InGaAs TFETs were formed by selective diffusion from Z-doped SOG [5], which can automatically realize the steep Zn profile, thanks to the concentration-dependent diffusion constant of Zn in InGaAs. We have combined this source with InGaAs quantum well (QW) channels, resulting in enhanced Ion and suppressed Ioff of n-TFETs [6, 7]. The minimum S.S. of 54 mV/dec. has been obtained at room temperature for the In0.53Ga0.47As /In0.67Ga0.33As/In0.53Ga0.47As QW n-TFETs having W/HfO2/Al2O3 gate stacks with CET of 1.4 nm. Type-II hetero-structure GaAsSb/InGaAs TFETs are also regarding as one of the most promising material systems for TFETs. We experimentally observed the operation of vertical n-TFETs with InGaAs channels and GaAsSb sources doped in an in-situ manner during the epitaxial growth, which also realized the steep impurity profiles [8]. While high leakage current in the source junctions degrades the performance at 300 K, TFETs with the high GaAsSb source doping concentration of 1x1020 cm-3 have exhibited the Ion/Ioff ratio of 109, the minimum SS of ~30 mV/dec. and Ion of ~4 mA/mm at 20 K. We have also confirmed the operation of GaAsSb/InGaAs n-TFETs on a Si wafer, which was fabricated by direct wafer bonding [4]. This work was supported by JST-CREST Grant Number JPMJCR1332, Japan, and a Grant-in-Aid for Scientific Research (17H06148) from MEXT. The authors would like to thank Drs. M. Yokoyama, O. Ichikawa, H. Yamada and T. Yamamoto in Sumitomo Chemical Corporation, Drs. M. Mitsuhara, H. Sugiyama, Hoshi and H. Yokoyama in NTT for their collaborations.

Low-Temperature RF Plasma Treatment Effect on Junctionless Pd-Al2O3-Ingaas Misfet Operation

The junctionless (JL) device concept for silicon-on-insulator MOSFETs was introduced by Colinge et al. in 2010 [1], demonstrating considerable gains in terms of process simplicity when compared to conventional inversion-mode MOSFETs. The objective of this work is to implement the JL device concept in an In0.53Ga0.47As channel, where the SiO2 insulator in [1] is replaced by a wider bandgap p-type In0.52Al0.48As barrier layer and to investigate the effect of low-temperature RF hydrogen plasma treatment on the main electrical parameters of such devices. The JL device architecture is particularly well suited to III-V channel materials. Firstly, the high doping concentration (Nd) present in the channel of a JL MOSFET is less problematic for In0.53Ga0.47As than it is for Si. Indeed, the bulk electron mobility in Si is ~100 cm2/V·s at Nd = 1×1019 cm-3, while in In0.53Ga0.47As the bulk mobility is ~4,000 cm2/V·s at a similar Nd level. Moreover, the JL architecture circumvents the difficulties associated with the implantation or regrowth techniques generally used to form the source/drain (S/D) regions of III-V inversion-mode MOSFETs. However in order to form a good Ohmic S/D contacts it is necessary to anneal the device at 350-400°C that could lead to diffusion of In atoms into the gate dielectric. In this work low-temperature RF plasma treatment (RFPT) [2] is proposed to improve S/D contacts and enhance the properties of JL MOSFETs. A structure consisting of a 32-nm-thick n- In0.53Ga0.47As (Nd = 2×1018 cm-3) on a 500-nm-thick p-In0.52Al0.48As (Na = 8×1015 cm-3) barrier was grown by metal organic vapour-phase epitaxy (MOVPE) on a p+-InP wafer (Fig. 1 (a)). In order to form a channel for the JL devices, the In0.53Ga0.47As layer was thinned using a 10% H2O2/10% HCl digital wet etching process to achieve channel thicknesses of 24, 20 and 16 nm. A gate enclosed device layout was employed to simplify the fabrication process flow (Fig. 1(b-e)). A surface passivation in 10% (NH4)2S for 30 min was performed before atomic layer deposition (ALD) of an 8.5-nm-thick Al2O3 gate oxide. A Pd gate was formed by e-beam evaporation and lift-off. The Al2O3 on the S/D contact areas was etched in dilute HF. The S/D contact formation was performed by e-beam evaporation of a Au/Ge/Au/Ni/Au stack and lift-off. The RFPT (13.6 MHz) was performed in forming gas (10%H2+90%N2) with additional heating of the sample holder (up to 200°C). Temperature of the samples at the RFPT did not exceed 250°C [2]. Well behaved Id-Vg characteristics measured on the 24-nm-thick In0.53Ga0.47As channel device are shown in Fig. 2. A threshold voltage (VT) of -0.55 V was extracted using the second-derivative method. Scaling the In0.53Ga0.47As channel thickness down to 16 nm improved the subthreshold swing (SS) but degraded the maximum Id and ION/IOFF due to the combined effect of S/D series resistance (RSD) and mobility degradation. As a result, the lowest SS value (115 mV/dec) was extracted on the 16-nm-thick In0.53Ga0.47As channel device and 190 mV/dec - on the 24-nm-thick In0.53Ga0.47As channel one, but the highest ION/IOFF value (1.5×105) was obtained on the 20-nm-thick In0.53Ga0.47As channel device and 2.0×104 - on the 24-nm-thick In0.53Ga0.47As channel one. The gate-to-channel Cgc-Vg characteristic featured a low frequency dispersion near the accumulation region, suggesting a low density of interface traps (Dit) in the upper part of the In0.53Ga0.47As bandgap. Moreover, the conductance analysis yielded low Dit values ranging from 1.5×1012 to 3.5×1012 cm-2×eV-1 from the conductance band edge to midgap, correspondingly. Measurements of RSD on circular transfer length method (CTLM) structures yielded the value of 12 kOhm on the 20-nm-thick In0.53Ga0.47As channel devices and contacts were strongly rectifying. RF plasma treatment with power 0.5 W/cm2 at 150°C resulted in Ohmic SD contact, a strong decrease of RSD down to 45 Ohm (Fig. 3) and increases the ION by two orders of magnitude (Fig. 2). Additionally, SS for the plasma treated devices decreases from 190 mV/dec to 150 mV/dec, and the threshold voltage shifts to positive values by 0.4 V (Fig.2). This is associated, correspondingly, with a decrease of Dit and negative charge in the gate dielectric. The conductance analysis yielded reduction of Dit at midgap down to 1.0×1012 cm-2×eV-1. [1] Colinge J.-P., Lee C.-W., Afzalian A., Akhavan N.D., Yan R., Ferain I., Razavi P., O'Neill B., Blake A., White M., Kelleher A.-M., McCarthy B., Murphy R. Nanowire Transistors Without Junctions. Nature Nanotechnology. Vol. 5, P. 225-229 (2010). [2] Nazarov A.N., Lysenko V.S., Nazarova T.M. Hydrogen Plasma Treatment of Silicon Thin-film Structures and Nanostructured Layers. Semiconductor Physics, Quantum Electronics & Optoelectronics. Vol. 11, P. 101-123 (2008). Figure 1

Tunnel FETs for ultra low Power Nanoscale Devices

Future ICs are facing dramatic challenges in performance as well as static and dynamic power consumption, which could be overcome using disruptive concepts, device architectures, technologies and materials. Promising solutions includes III-V channels, heterojunctions, 2D layers, multi-gates structures, nanowires (NWs), tunnel FETs (TFETs), ferroelectric FETs (Fe-FETs), and hybrid devices. In the domain of small slope switches, which are very interesting for ultra low power operation, TFETs, Fe-FETs and hybrid devices seem very promising. Thus far, no one has experimentally demonstrated a TFET that has simultaneously both a CMOS-competitive driving current Ion and a sub-60 mV/decade subthreshold swing over several decades. But recently, substantial improvements of TFET and hybrid device performance have been reported, showing that these novel device architectures using new materials and carrier transport could be used for several applications.

(Invited) Transistor Applications Using Vertical III-V Nanowires on Si Platform

III-V compound semiconductor nanowires (NWs) have stimulated interest in recent years because of their unique properties and potential applications as building blocks for nanoscale electronic and photonic devices. For future electronics, inherent issue for low-power LSI is lowering supply voltage of transistor while avoiding physical limit of subthreshold slope (SS = 2.3 k BT/q = 60 mV/dec). Otherwise, this limitation will stop further scaling of the power consumption even if a multi-gate architecture and III-V/Ge channels are implemented. In this talk we report on new tunnel junction based on III-V/Si interface [1,2] which is formed by selective-area growth of III-V nanowires (NWs) on Si [3-5], and demonstrated vertical TFETs with steeper SS[6,7]. This new tunnel junctions can inherently forms abrupt heterojunction regardless of precise doping because the band discontinuity is determined only by the offset of each III-V and Si. Thus, good gate-electrostatic control and depletion-width control for the tunnel transport is defined only by the III-V channel region regardless of degeneration of source materials. For integration of III-V NWs on Si, selective-area growth has no thick buffer layer, thus the III-V NWs/Si interface is able to show unique band structures. The narrow gap III-Vs such as InAs and In0.7Ga0.3As NWs, for instance, exhibits staggered-Type II band structure when the n-type NWs are formed on p-Si substrates regardless precise doping. Thus, we integrated InGaAs NWs on Si substrate by utilizing specific growth sequence to align vertical NWs [6]. Sn was used for n-type dopant, and Zn-pulse doping technique [7] was used to make pseudo intrinsic layer as channel region. The formation of intrinsic layer in such small NW-volume would be very important to induce large internal electrical field at the InGaAs/Si heterojunction. The length of the Zn-pulse doped region correspond to channel-length (200 nm-long in this case). Next, we demonstrate electronic devices using III-V NWs on a Si substrate. Fabricated vertical transistors contained In0.7Ga0.3As NWs with modulation doped layer. We observed n-type FET behavior in ID-VDS and ID-VG characteristics. The performances are threshold voltage ~ 0.25 V, Gm,max = 1.45 µS/µm at VDS = 0.50 V, Ion / Ioff > 106, subthreshold slope, SS = 78 mV/decade. Besides the III-V NW-based vertical FETs, the heterointerface between the III-V NWs and Si can be used as tunnel FETs (TFETs). In this case, we use band discontinuity between III-V NWs and Si substrate for TFETs. The device fabricated by InAs NW on Si substrate showed switching behavior with an average subthreshold slope (SS) of 30 mV/dec, which is much lower than the physical limitation of metal-oxide-semiconductor field-effect transistors (MOSFETs, SS ~ 60 mV/dec.) [8,9]. Reducing the opening diameter of the masked substrate decreased the numbers of misfit dislocations. The TFETs made by using III-V NW/Si heterojunctions demonstrated steep-SS properties at room temperature. One of the key issues in the vertical TFETs is the formation of intrinsic channels inside the tiny NW-body and another is the reduction of NW-diameter. We also discuss several current-boosting technologies for the TFETs. The current-boosted TFET exhibits steep SS and high Ion, and the transconductance efficiency (Gm/ID), which is important parameter for low-power analog circuits, is a thousand times higher than that of conventional MOSFETs [10]. References 1) K. Tomioka and T. Fukui, Appl. Phys. Lett., 98, 083114-1 – 3 (2011). 2) K. Tomioka and T. Fukui, Appl. Phys. Lett., 104, 073507-1 – 4 (2014). 3) K. Tomioka et al., Nano Lett., 8, 3475 – 3480 (2008). 4) K. Tomioka et al., Nanotechnology, 20, 145302 – 145309 (2009) 5) K. Tomioka et al., Nature, 488, 189 – 192 (2012). 6) K. Tomioka et al., Nano Lett., 13, 5822 – 5826 (2013) 7) E. Nakai et al., Jpn. J. Appl. Phys., 54, 015201-1 – 3 (2015). 8) K. Tomioka et al., IEEE IEDM Tech. Dig. 88 – 91 (2013). 9) K. Tomioka et al., IEEE ESSDERC Tech. Dig. 397 – 402 (2016). 10) K. Tomioka et al., paper submitted

(Invited) Transistor Applications Using Vertical III-V Nanowires on Si Platform

Vertical III-V nanowire (NW) is a promising channel material for high-speed switching devices in future integrated circuits because surrounding-gate structures have good electrostatic gate controllability while suppressing inherent large leakage current in III-V channels and outperform lateral switching devices in terms of power consumption while keeping good scalability. As for the integration of III-V NWs on Si, direct integration of vertical III-V NWs by selective-area growth has advantages for high -performance transistor applications because of position/size-uniformity and core-shell structure with modulation doping.

Modeling of Charge and Quantum Capacitance in Low Effective Mass III-V FinFETs

In this paper, we present a compact model for semiconductor charge and quantum capacitance in III-V channel FETs. With III-V being viewed as the most promising candidate for future technology node, a compact model is needed for their circuit simulation. The model presented in this paper addresses this need and is completely explicit and computationally efficient which makes it highly suitable for SPICE implementation. The proposed model is verified against the numerical solution of coupled Schrodinger–Poisson equation for FinFET with various channel thickness and effective mass.

(Invited) Recent Progress in Vertical Si/III-V Tunnel FETs: From Fundamentals to Current-Boosting Technology

Inherent issue for low-power LSI is lowering supply voltage of transistor while beating physical limit of subthreshold slope (SS = 2.3 k BT/q = 60 mV/dec) [1]. Otherwise, this limitation will stop further scaling of the power consumption even if a multi-gate architecture and III-V/Ge channels are implemented [2-4]. The steep-slope transistors such as tunnel FETs (TFETs) and impact ionization FETs have therefore been proposed to overcome the limitation and to reduce supply voltage to sub-0.5 V in future LSI. The tunneling transistors are most promising switching devices because of possibility for lower SS than 60 mV/dec. and better compatibility with conventional integration process. However, there are some difficulties in decreasing SS while increasing tunneling current as high as that of conventional FETs. Recently, we reported on new tunnel junction based on III-V/Si interface [4,5] which is formed by selective-area growth of III-V nanowires (NWs) on Si [6-8], and demonstrated vertical TFETs with steeper SS [9,10]. This new tunnel junctions can inherently forms abrupt heterojunction regardless of precise doping because the band discontinuity is determined only by the offset of each III-V and Si. Thus, good gate-electrostatic control and depletion-width control for the tunnel transport is defined only by the III-V channel region regardless of degeneration of source materials. Here we report on recent progress in the vertical TFETs using III-V NW/Si heterojunction and discuss some current-boosting technology such as strain and other technique. As for integration of III-V NWs on Si, selective-area growth has no thick buffer layer, thus the III-V NWs/Si interface is able to show unique band structures. The narrow gap III-Vs such as InAs and In0.7Ga0.3As NWs, for instance, exhibits staggered-Type II band structure when the n-type NWs are formed on p-Si substrates regardless precise doping [4,5]. Thus, we integrated InGaAs NWs on Si substrate by utilizing specific growth sequence to align vertical NWs [8]. Sn was used for n-type dopant, and Zn-pulse doping technique [10] was used to make pseudo intrinsic layer as channel region. The formation of intrinsic layer in such small NW-volume would be very important to induce large internal electrical field at the InGaAs/Si heterojunction. The length of the Zn-pulse doped region correspond to channel-length (200 nm-ling in this case). The vertical TFET with a single vertically aligned n+-InGaAs/Zn-pulse doped InGaAs axial NW on a p-Si substrate was firstly demonstrated. The device process was reported elsewhere [4,5]. The channel length was 200 nm. In the TFET using the bare InGaAs NW, the tunneling current under revise bias was modulated by gate bias with SS of 80 – 90 mV/dec, and the ION was 2.7 nA/µm at VDS = 0.50 V. With decreasing VDS, the SS become steeper than 60 mV/dec. at low drain current region. The minimum SS was around 50 mV/dec. at VDS= 0.10 V. As for current boosting technology, channel length scaling was characterized [5]. The ION was 100 times enhanced with decreasing the channel length to 50 nm, and the SS decreased to 30 mV/dec. at VDS = 0.10 V. This indicated that the drain end should be close to the tunnel junction width. Next, strain effect was characterized by using InGaAs/InP core-shell nanowire structure. Switching behavior with a SS of 42 mV/dec was obtained under reverse bias direction. This switching characterization appeared at as low as VDS of 10 mV. The SS of the TFET exhibits steeper SS behavior under various VDS. The ION for InGaAs/InP core-shell NW/Si TFET was 10 times higher than that of the bare InGaAs NW/Si TFET. The benefit of InP shell layer is improvement of SS and enhancement of ION. The InP shell layer act as passivation effect on the semiconductor/oxide interface. TEM analysis revealed the large compressive strain was induced at the near InGaAs NW/Si, which ascribes that the uniaxial compressive strain decrease effective band gap of InGaAs/Si while enhancing tunneling probability. Reduction in effective band gap of tunnel junction can partly enhance the tunneling current, but the tunneling leakage at source/channel region was increased degrading SS. Thus, further additional technology to enhance the tunneling current will be discussed.

III-V族チャネルを持つMOSFET

Present status of III-V channel MOSFET is reported. Progress of Si MOSFET requires successive technology boosters and next candidate as technology booster is high mobility channel. In case of Ge, sufficient contact cannot be obtained in n-MOSFET. Thus, III-V channel became the candidate of high mobility channel in n-MOSFET. At present, interface state density around 1×1012 eV -1cm-2 by using ALD, high current density > 2 A/mm @VDD=0.5 V are reported. Formation of InGaAs film on large scale Si wafer is also reported. However, ultrathin channel taking short channel effect into account degrades mobility. Multi-gate FET and improvement of MIS interface are required for realization of high on-current in short channel devices.