III-V Channel Materials Research Articles

(Invited) Wet-Chemical Etching of III-V Semiconductors: Towards Atomic-Layer-Scale Processing

Recent developments in device technology resulted in an upsurge of interest in III-V compound semiconductors. These include improved fabrication techniques for flexible electronic devices,[1,2] and epitaxial integration of various III-V channel materials on Si-based platform wafers enabling the development of highly scaled CMOS transistors [3–5] and nanophotonic devices [6]. While fabrication strategies for traditional III-V optoelectronic devices such as light-emitting diodes, lasers and solar cells are well established, the very small dimensions of these new nanodevices pose new problems. In such applications wet-chemical etching remains an essential step. The ever decreasing size of III-V devices requires ultimately atomic-layer-scale control of surfaces in terms of etching selectivity, stoichiometry and morphology.[7,8] Considerable expertise and literature is currently available on III-V semiconductor etching[9,10]. However, much of the reported work is empirical, etch rates are high, and mechanistic insight into (electro)chemical processes occurring at the semiconductor-solution interface is often lacking. In this work an overview will be given of wet-chemical approaches for nanoscale and atomic-layer-scale etching of Ga(In)As and InP. Two types of etching systems will be discussed. The first is based on the use of acidic H2O2 solution. Inductively coupled plasma mass spectrometry (ICP-MS) measurements, used to determine etching kinetics, showed that under similar conditions the etch rate of Ga(In)As in H2SO4/H2O2 solution is more than an order of magnitude higher than that of InP. Another striking observation is the influence of the acid, H2SO4 and HCl, on etching kinetics. An increase in HCl concentration leads to an increase in the etch rate of InP while the dissolution rate of Ga(In)As is markedly lowered for the active etching range. Previous work suggested that the surface oxide or hydroxide may be important.[11,12] We have used X-ray photoemission spectroscopy (XPS) and time-of-flight elastic recoil detection analysis (ToF-ERDA) to obtain information about (hydr)oxide formation on the etched surfaces. ToF-ERDA measurements also allowed us the detect surface chlorine in the case of HCl-based etchants. The results indicate that, while the initial step (the breaking of the III-V surface bond) is the same for both semiconductors, the ease with which the resulting group V hydroxide entity at the surface can be deprotonated determines whether the etch rate will be high (Ga(In)As) or low (InP). The mechanism can also help to explain the contrasting role of HCl in the dissolution of the two semiconductors. An alternative digital type of etching approach for InGaAs and InAs involves self-limiting surface oxidation in O3/H2O followed by an oxide removal step in HCl solution[12]. ICP-MS quantification of the dissolved surface oxide species indicates that a high stoichiometry of etching is obtained and that the number of equivalent oxidized atomic layers can be controlled by adjusting the dissolved O3 concentration. For >4 cycles some surface roughening is observed, most likely due to due to the high solubility of As oxides in water. An important advantage of the 2-step approach is that defect selective etching can be effectively suppressed. Examples of applications of the two etching systems will be highlighted. [1] C.-W. Cheng, K.-T. Shiu, N. Li, S.-J. Han, L. Shi, D.K. Sadana, Nat. Commun. 4 (2013) 1577. doi:10.1038/ncomms2583[2] N.J. Smeenk, J. Engel, P. Mulder, G.J. Bauhuis, G. Bissels, J.J. Schermer, E. Vlieg, J.J. Kelly, ECS J. Solid State Sci. Technol. 2 (2013) P58–P65.[3] J.A. del Alamo, Nature. 479 (2011) 317–323. doi:10.1038/nature10677[4] M. Paladugu, C. Merckling, R. Loo, O. Richard, H. Bender, J. Dekoster, W. Vandervorst, M. Caymax, M. Heyns, Cryst. Growth Des. 12 (2012) 4696–4702. doi:10.1021/cg300779v[5] N. Waldron, C. Merckling, L. Teugels, P. Ong, S.A.U. Ibrahim, F. Sebaai, A. Pourghaderi, K. Barla, N. Collaert, A.V.-Y. Thean, IEEE Electron Device Lett. 35 (2014) 1097–1099. doi:10.1109/LED.2014.2359579[6] Y. Shi, Z. Wang, J. Van Campenhout, M. Pantouvaki, W. Guo, B. Kunert, and D. Van Thourhout, Optica 4, 1468-1473 (2017). doi:10.1364/OPTICA.4.001468[7] K.J. Kanarik, T. Lill, E.A. Hudson, S. Sriraman, S. Tan, J. Marks, V. Vahedi, R.A. Gottscho, J. Vac. Sci. Technol. Vac. Surf. Films. 33 (2015) 020802. doi:10.1116/1.4913379[8] G.S. Oehrlein, D. Metzler, C. Li, ECS J. Solid State Sci. Technol. 4 (2015) N5041–N5053. doi:10.1149/2.0061506jss[9] P.H.L. Notten, J.E.A.M. Meerakker, J.J. Kelly, Elsevier Advanced Technology, 199.[10] A.R. Clawson, Mater. Sci. Eng. R Rep. 31 (2001) 1–438[11] D.H. van Dorp, S. Arnauts, D. Cuypers, J. Rip, F. Holsteyns, S.D. Gendt, J.J. Kelly, ECS J. Solid State Sci. Technol. 3 (2014) P179–P184. doi:10.1149/2.021405jss[12] D.H. van Dorp, S. Arnauts, F. Holsteyns, S.D. Gendt, ECS J. Solid State Sci. Technol. 4 (2015) N5061–N5066. doi:10.1149/2.0081506jss

Effect of Low Temperature RF Plasma Treatment on Electrical Properties of Junctionless InGaAs MOSFETs

In this paper, we study the effect of low-temperature RF plasma treatment in forming gas (10%H2+90%N2) on the electrical characteristics of junctionless MOSFETs with n-In0.53Ga0.47As channel and an Al2O3 gate dielectric. The impact of plasma power density on the device parameters is investigated. It is found that RF plasma annealing with a low power density (0.5 W/cm2) at 150°C for 10 min provides substantial improvement of source/drain contacts resistance and the carrier mobility resulting in a considerable increase of the on-state current and transconductance. It also improves the subthreshold slope and reduces the fixed positive charge in Al2O3 under the gate, shifting the threshold voltage toward positive values. It is demonstrated that non-thermal factors play a principle role in modification of electrical properties of the JL MOSFETs under RF plasma treatment. Such treatment may be an efficient tool for the improvement of the performance of the advanced MOSFETs with III-V channel materials.

Geometric structure and electronic properties of wurtzite GaN/HfO2 interface: A first-principles study

III-V interface with high-k oxide, especially HfO2, is crucial to the development of high mobility microelectronic devices. In this work, we systematically investigated the wurtzite GaN/cubic HfO2 interface based on the first-principles calculations with density functional theory in terms of the geometric structure and electronic properties. In order to mimic the high-k growth conditions, the interfacial oxygen contents in the slab interface models varied to study the interface stability and the relevant electronic structures. It is found that the oxygen rich interface, i.e., oxygen content of 83.3% (O5), shows the most stability in a large range of the oxygen chemical potential from 0 eV to −4.34 eV. Through the calculations of local density of states and Bader charge analysis, we noticed that increasing the interfacial oxygen content leads to the increase of the valence band offset (VBO) and the decrease of the conduction band offset (CBO), respectively. More importantly, interface O5 displays a promising VBO (0.86 eV) and CBO (1.34 eV), which meets the industrial requirements to confine the carrier in the III-V channel materials. Furthermore, no interfacial gap states are observed in interface O5, indicating that O5 is free of Fermi level pinning. This theoretical exploration suggests that varying oxygen content at the interface could result in the optimal interface for the applications of high mobility electronic devices.

Low-Temperature RF Plasma Treatment Effect on Junctionless Pd-Al2O3-Ingaas Misfet Operation

The junctionless (JL) device concept for silicon-on-insulator MOSFETs was introduced by Colinge et al. in 2010 [1], demonstrating considerable gains in terms of process simplicity when compared to conventional inversion-mode MOSFETs. The objective of this work is to implement the JL device concept in an In0.53Ga0.47As channel, where the SiO2 insulator in [1] is replaced by a wider bandgap p-type In0.52Al0.48As barrier layer and to investigate the effect of low-temperature RF hydrogen plasma treatment on the main electrical parameters of such devices. The JL device architecture is particularly well suited to III-V channel materials. Firstly, the high doping concentration (Nd) present in the channel of a JL MOSFET is less problematic for In0.53Ga0.47As than it is for Si. Indeed, the bulk electron mobility in Si is ~100 cm2/V·s at Nd = 1×1019 cm-3, while in In0.53Ga0.47As the bulk mobility is ~4,000 cm2/V·s at a similar Nd level. Moreover, the JL architecture circumvents the difficulties associated with the implantation or regrowth techniques generally used to form the source/drain (S/D) regions of III-V inversion-mode MOSFETs. However in order to form a good Ohmic S/D contacts it is necessary to anneal the device at 350-400°C that could lead to diffusion of In atoms into the gate dielectric. In this work low-temperature RF plasma treatment (RFPT) [2] is proposed to improve S/D contacts and enhance the properties of JL MOSFETs. A structure consisting of a 32-nm-thick n- In0.53Ga0.47As (Nd = 2×1018 cm-3) on a 500-nm-thick p-In0.52Al0.48As (Na = 8×1015 cm-3) barrier was grown by metal organic vapour-phase epitaxy (MOVPE) on a p+-InP wafer (Fig. 1 (a)). In order to form a channel for the JL devices, the In0.53Ga0.47As layer was thinned using a 10% H2O2/10% HCl digital wet etching process to achieve channel thicknesses of 24, 20 and 16 nm. A gate enclosed device layout was employed to simplify the fabrication process flow (Fig. 1(b-e)). A surface passivation in 10% (NH4)2S for 30 min was performed before atomic layer deposition (ALD) of an 8.5-nm-thick Al2O3 gate oxide. A Pd gate was formed by e-beam evaporation and lift-off. The Al2O3 on the S/D contact areas was etched in dilute HF. The S/D contact formation was performed by e-beam evaporation of a Au/Ge/Au/Ni/Au stack and lift-off. The RFPT (13.6 MHz) was performed in forming gas (10%H2+90%N2) with additional heating of the sample holder (up to 200°C). Temperature of the samples at the RFPT did not exceed 250°C [2]. Well behaved Id-Vg characteristics measured on the 24-nm-thick In0.53Ga0.47As channel device are shown in Fig. 2. A threshold voltage (VT) of -0.55 V was extracted using the second-derivative method. Scaling the In0.53Ga0.47As channel thickness down to 16 nm improved the subthreshold swing (SS) but degraded the maximum Id and ION/IOFF due to the combined effect of S/D series resistance (RSD) and mobility degradation. As a result, the lowest SS value (115 mV/dec) was extracted on the 16-nm-thick In0.53Ga0.47As channel device and 190 mV/dec - on the 24-nm-thick In0.53Ga0.47As channel one, but the highest ION/IOFF value (1.5×105) was obtained on the 20-nm-thick In0.53Ga0.47As channel device and 2.0×104 - on the 24-nm-thick In0.53Ga0.47As channel one. The gate-to-channel Cgc-Vg characteristic featured a low frequency dispersion near the accumulation region, suggesting a low density of interface traps (Dit) in the upper part of the In0.53Ga0.47As bandgap. Moreover, the conductance analysis yielded low Dit values ranging from 1.5×1012 to 3.5×1012 cm-2×eV-1 from the conductance band edge to midgap, correspondingly. Measurements of RSD on circular transfer length method (CTLM) structures yielded the value of 12 kOhm on the 20-nm-thick In0.53Ga0.47As channel devices and contacts were strongly rectifying. RF plasma treatment with power 0.5 W/cm2 at 150°C resulted in Ohmic SD contact, a strong decrease of RSD down to 45 Ohm (Fig. 3) and increases the ION by two orders of magnitude (Fig. 2). Additionally, SS for the plasma treated devices decreases from 190 mV/dec to 150 mV/dec, and the threshold voltage shifts to positive values by 0.4 V (Fig.2). This is associated, correspondingly, with a decrease of Dit and negative charge in the gate dielectric. The conductance analysis yielded reduction of Dit at midgap down to 1.0×1012 cm-2×eV-1. [1] Colinge J.-P., Lee C.-W., Afzalian A., Akhavan N.D., Yan R., Ferain I., Razavi P., O'Neill B., Blake A., White M., Kelleher A.-M., McCarthy B., Murphy R. Nanowire Transistors Without Junctions. Nature Nanotechnology. Vol. 5, P. 225-229 (2010). [2] Nazarov A.N., Lysenko V.S., Nazarova T.M. Hydrogen Plasma Treatment of Silicon Thin-film Structures and Nanostructured Layers. Semiconductor Physics, Quantum Electronics & Optoelectronics. Vol. 11, P. 101-123 (2008). Figure 1

(Invited) ALD Materials for the Integration of III-V Based Transistors

III-V compound semiconductors are considered promising transistor channel materials to enable scaling beyond Si technology due to their high bulk electron mobility values. However, unlike Si, III-V materials have comparatively poor quality oxides and the interface between commonly utilized high-k dielectrics and the III-V channel surface is problematic. Engineering the high-k gate stack remains one of the main technical challenges to integration of III-V materials in Si-based CMOS technology. Silicon dioxide (SiO2) forms an extremely high quality interface with Si and features a high bandgap (9eV) which effectively screens channel electrons from the effects of oxide traps in bulk high-k materials (e.g., hafnium oxide) which degrade electron mobility. However, unlike Si, III-V materials possess poor quality native oxides with a very high density of oxide traps, which thus prove unsuitable as channel dielectrics due to the resultant high density of interface states (Dit). Formation of these oxides must be prevented, making surface preclean and chemical passivation techniques critical. In addition, an alternative IL is required prior to deposition of the primary high-k dielectric to reduce the impact of oxide traps while also maintaining a low Dit. Optimization of the primary high-k deposition process itself may also be required. Due to the ultra-thin layers and moisture / oxygen sensitive materials in question, in-situ processing without air exposure throughout the gate dielectric sequence is beneficial, if not mandatory. Various approaches have been introduced to passivate the III-V surface prior to dielectric deposition to achieve reduced interface states. Sulfur passivation via immersion in wet chemical (NH4)2S solutions has been the most studied, with demonstration of promising interface properties. However, this approach is difficult to integrate into a vacuum deposition system, resulting in unavoidable air exposure time following sulfur passivation. To address the limitations of wet chemical processing, an innovative in-situ sulfur passivation approach is described here. In this approach, the sulfur precursor is delivered in vapor form from either (NH4)2S solution or compressed H2S gas cylinder in-situ to a hot walled cross flow ASM Pulsar® 3000 ALD reactor such that the high-k layers can be deposited immediately following passivation without air exposure. In-situ vapor passivation treatments yield higher [S] than solution-based passivation techniques per XPS analysis. Passivated samples exhibit improved C-V characteristics, and lower dispersion values compared to the HCl etched reference for planar MOSCAPS. The Ditvalues for in-situ passivated samples were reduced to ~1-2x1012 /cm2eV, promising for application to high mobility transistors. SiO2 is a candidate IL for III-V gate stacks due to its high bandgap and low density of oxide traps, but a high quality atomic layer deposited SiO2 film without significant channel oxidation has not been demonstrated on Si, let alone III-V materials, to date. The incorporation of Si into another metal oxide (e.g., Al2O3) is thus an interesting approach for evaluation. Two H2O-based ALD processes for aluminum silicate (Al1-xSixO) were developed using an ASM Pulsar®. Trimethylaluminum (TMA) and aluminum chloride (AlCl3), have been compared as Al precursors with silicon tetrachloride (SiCl4) as the Si precursor. The TMA-based process exhibits a measureable level of C incorporation (2-3%), while [C] in the AlCl3-based process was below detection limits due to halide chemistries utilized. Parasitic C in the TMA-based IL is projected to be a contributor to oxide defects resulting in degraded electrical performance as compared to the pure halide-based process. The impact of other factors such as deposition temperature and pulsing sequence were also studied, and the ALD growth mechanisms for these two processes are discussed in further detail. Ultimately, Al2O3-based materials and other commonly investigated high-k metal oxides appear limited in ability to meet the performance requirements for a robust III-V channel transistor, although incremental improvements have been demonstrated. As such, alternative ALD materials have been extensively explored for application to III-V channel materials. Recent development has resulted in demonstration of a low temperature thermal ALD process of a novel material which exhibits strong potential for application as IL in III-V channel devices. The IL material is also deposited using an ASM Pulsar® reactor, following S passivation and prior to deposition of HfO2 high-k bulk dielectric. Dit values <1E12, low dispersion (<1%) and hysteresis (<30 mV) values have been demonstrated. Current device performance equals previously published benchmark device metrics for InGaAs channel devices. We projected that device performance can be further improved via optimization of the in-situ passivation and ALD process parameters for the novel interface layer and bulk high-k.

Annealing Effects on the Electrical Activation of Si Dopants in InGaAs

There is a renewed interest in integrating high mobility III-V channel materials into sub 10 nm nMOS devices but the continued scaling of devices has resulted in the need to create contacts and source/drains with ultra low contact resistivities in order to reduce current losses. This study investigates thermal stability of Si dopants incorporated via MBE growth and ion implantation as potential methods to create heavily-doped, low resistance source/drain regions in III-V channel devices. For this study, the electrical activation and diffusion of Si active layers in In0.53Ga0.47As formed by a 10 keV, 5×1014 cm-2 Si implant and MBE growth doping with a peak Si concentration of 7×1019 cm-3 were investigated as a function of post growth and post-implant isochronal annealing. While most previous studies conclude that MBE doping can achieve higher active Si concentrations than ion implantation, the results of this study show conclusively that electrically active Si concentrations above 1.4×1019 cm-3 formed by MBE doping are prone to deactivation upon thermal treatment after growth whereas ion-implantation shows no metastable activation behavior. Significant Si deactivation in MBE doped substrates is shown to occur before the onset of Si diffusion whereas saturated activation in ion implanted substrates does not occur until diffusion is observed. Upon annealing at sufficiently high temperatures to cause Si diffusion, the electrical activation of Si in MBE doped substrates and ion implanted Si are shown to converge to a stable activation limit of 1.4×1019 cm-3. The common activation limit upon Si profile motion for both Ion implanted and growth doped Si active layers after thermal annealing at 750°C suggests that the maximum stable electrical activation of Si is an intrinsic property of In0.53Ga0.47As. Si diffusivity has also been calculated from SIMS results in both ion-implanted substrates and growth-doped substrate and Si diffusion in MBE doped substrates was observed to be nearly three times as fast as ion implanted substrates presumably due to the observed concentration dependent diffusion effects. The mechanism of Si diffusion and its relation to the observed concentration dependent diffusion and electrical activation behavior in both materials are also discussed. Figure 1

A comparative TCAD assessment of III-V channel materials for future high speed and low power logic applications

In this work, by means physics based drift-diffusion simulations, three different narrow band gap semiconductors; InAs, InSb and In0.53Ga0.47As, and their associated heterostructures have been studied for future high speed and low power logic applications. It is observed that In0.53Ga0.47As has higher immunity towards short channel effects with low DIBL and sub-threshold slope than InSb and InAs. Also it is observed that for the same device geometry InSb has the highest drive current and lower intrinsic delay but its ION/IOFF figure of merit is deteriorated due to excess leakage current.

Engineering the III-V Gate Stack Properties by Optimization of the ALD Process

The passivation of the interface between the IIIV substrate and the high-k is key in order to bring these materials into the 7nm technology node. A high amount of interface states (Dit>1E13 /cm2eV) will trap the electrons resulting in a reduced mobility and degraded subtreshold slope[1]. Additional defects present in the oxide near the IIIV interface will generate device instabilities[2]. The goal should be to reduce the amount of oxide traps below 1.5E10/cm2at an operating field of 3.5E6 V/cm in order to meet the 10 years reliability target. In this paper, it will be shown that careful engineering of the ALD process can yield a high quality interface at low CET values (<1.5nm). However, the bulk oxide trapping behavior is not changed accordingly with the ALD process and further improvement is required.TMA prepulsing, H2S exposure as well as the incorporation of a thin ALD rare earth (RE) oxide layer have been studied as a way to reduce the Dit level at the In0.53Ga0.47As/high-k interface. In addition, we present the oxide trap behavior for these different pretreatment/high-k combinations.TMA prepulsing has been reported to improve the interface quality of the In0.53Ga0.47As/ high-k interface[3]. We have studied the influence of the TMA pulse length in combination with ALD Al2O3 (TMA/H2O), HfO2 (HfCl4/H2O) and AlSiOx (TMA based and C-free process). For a 4nm Al2O3 layer, an optimal Dit is obtained when the TMA pulse length is increased from the standard 0.1 s up to 5 s during the first 5 ALD cycles (Figure 1). For a higher number of cycles with long TMA pulses, the Dit level increases again. This could be attributed to the increase of unreacted –CH3 groups as the H2O pulses were kept the same as compared to the standard TMA pulse length. Similar behavior can be found with a 4nm HfO2 stack: pretreatment of the interface with 5 cycles (TMA/H2O purge) with a 5s TMA pulse lowers the Dit by a factor ~2 compared to no pretreatment.The idea of using AlSiOx is to slow down the oxide trap response because of a possible higher Ec offset to the InGaAs channel. The incorporation of Si into the Al2O3 stack is accompanied with a Dit reduction, but at the expense of a CET increase. Again, prepulsing with TMA lowers the Dit level as seen with the Al2O3 process down to a midgap Dit of ~8E11 /cm2eV (see Figure 2). However, in the case of a C-free AlSiOx process, a Dit increase is accompanied when prepulsing with TMA. For this process, a S-terminated InGaAs surface lowers the Dit of the formed gate stack and a similar level of ~8E11 /cm2eV can be reached.Finally, the incorporation of RE-oxides as an interfacial passivation layer was studied for both Al2O3 (4nm) and HfO2 (4nm). Both Sc2O3 ((MeCp)3Sc/H2O) and Gd2O3 (i(PrCp)3Gd)/H2O) were studied and in each case, the insertion of 4 ALD cycles reduces the Dit. The lowest Dit level was observed for Gd2O3 (~2E12/cm2eV independent of the cap layer).The oxide trap behavior for several of these gate stacks was also studied. An H2S treatment improves the oxide trap behavior slightly (~2% reduction of oxide traps). Shifting from a TMA based AlSiOx process to a C-free AlSiOx process yields a reduction of a factor ~1.5. However, the range of oxide traps for all these stacks is higher than 5e11/cm2 at the target field, which is still 1 order of magnitude too high.We demonstrate that the final gate stack passivation is dependent on the interaction between the In0.53Ga0.47As surface termination and the ALD precursors. A long TMA prepulse seems to be beneficial for most of the gate stacks but the improvement cannot be generalized. We demonstrate that the pretreatments used for Dit optimization of the Al2O3 stack, can also be applied in combination with HfO2. This means that we can reach similar Dit levels with a HfO2 based stack using the right pretreatment with large reduction in CET. Despite this improvement on interface traps, the improvement on oxide traps is not substantial. A further reduction of interface traps, will not yield a proportional device improvement 1. However, a further reduction of oxide traps is a prerequisite in order to introduce the IIIV channel materials into the 7nm technology node.[1] G. Hellings et al, IEEE Transactions on Electron Devices, 58(4), (2011), 938-944.[2] D. Lin et al., IEDM, (2012), p645-648.[3] J.B. Clemens et al., J. Chem. Phys., 133, (2010), 154702.

(Invited) Gate Stacks for Silicon, Silicon Germanium, and III-V Channel MOSFETs

High-k gate dielectrics such as HfO2 and metal gate electrodes such as TiN have been deployed across a wide range of CMOS logic products in both the low-power (e.g., mobile) and the high-performance (e.g., server) space. Available device geometries include planar field-effect transistors on bulk Si, on partially depleted silicon-on-insulator (PDSOI), and on fully depleted SOI (FDSOI), as well as FinFETs. During the decade-long effort leading up to successful high-k/metal gate (HKMG) implementation, much has been learnt about the fundamental materials science underlying such gate stacks. Yet, research continues in order to ensure continued circuit density and performance scaling.After reviewing the gate-first and gate-last (or replacement gate) approaches to HKMG implementation, I will discuss device challenges that can be resolved by materials engineering on the atomic scale. A prime example is the threshold voltage (Vt) challenge, which is caused by charged oxygen vacancies in hafnium-based gate dielectrics formed at elevated temperatures, thus increasing pFET Vt. These vacancies can be filled by lateral or top-down oxidation. As an alternative, additional Vt-setting techniques can be employed, such as metal oxide capping layers (e.g., Al2O3 or La2O3 for pFET and nFET, respectively) that form permanent electrical dipoles, or SiGe channels (cSiGe) which modulate the band offsets while additionally providing a welcome hole mobility boost. A second example is continued equivalent oxide thickness (EOT) scaling. We have developed the approach of metal-gate-induced remote oxygen scavenging, which results in a thinning of the SiO2 layer at the high-k/channel interface. In this way, EOT of 0.4-0.5 nm can be reached for both nFET and pFET. I will in particular discuss our recent results on aggressive cSiGe pFET scaling (Fig. 1), including the dependence of hole mobility (Fig. 2) and of negative bias temperature instability (NBTI) reliability on EOT and thus on interfacial SiO2thickness [1].In the second part of my talk, I will show that HKMG not only provides the well-known gate-length scaling benefit through improved electrostatics, but it can also directly enable aggressive device pitch and density scaling through borderless (semi-self-aligned) source-drain (S/D) contacts [2]. Conventional gate-first high-k/metal gate (HKMG) CMOS technologies employ metal-inserted poly-Si stacks (MIPS) such as a-Si/TiN, where the amorphous Si serves as a precursor for low-sheet-resistance (Rs) self-aligned NiSi on the gates and as an oxygen barrier preventing high-k/Si interfacial SiO2 growth. A full metal gate (FMG, Fig. 3), instead containing a deposited low-Rs metal layer, can be encapsulated in a dielectric resistant to the S/D contact etch, resulting in borderless contacts. We have developed two FMG electrodes based on TiSix/TiN and W/TaMN/TiN (M = oxygen scavenging metal). With both FMG on Hf-based gate dielectrics, Si channel nFET and SiGe channel pFET parametrics and reliability similar to those of poly-Si/TiN control devices are achieved, with good EOT scalability [3,4].Finally, I will provide an outlook on high-k gate dielectrics for high-mobility III-V channel materials. Specifically, I will compare three interface approaches to InGaAs channel nFET gate stack formation. The first is based on direct high-k deposition onto InGaAs, while the other two approaches rely on the insertion of an amorphous Si or an epitaxial InP capping layer to passivate the InGaAs. The impact of such caps on interface trap density and scalability will be discussed.[1] M.M. Frank et al., ECS Solid State Lett. 2, N8 (2013).[2] S.-C. Seo, et al., VLSI, p. 36 (2011).[3] M. M. Frank et al., as discussed at SISC 2011.[4] M. M. Frank et al., as discussed at SISC 2013..

Border Traps in Ge/III–V Channel Devices: Analysis and Reliability Aspects

The aim of this review paper is to describe the impact of so-called border traps (BTs) in high- k gate oxides on the operation and reliability of high-mobility channel transistors. First, a brief summary of the physics of BTs will be given, describing the charge trapping and release in terms of the elastic tunneling model. It will be also pointed out how information on the BT properties can be extracted from popular measurement techniques such as low-frequency (1/f) noise and variable-frequency charge pumping. In the next two parts, the impact of BTs on metal-oxide-semiconductor structures fabricated on Ge or III-V channel materials is outlined, with particular emphasis on the development of novel or adapted measurement techniques such as AC transconductance dispersion or trap spectroscopy by charge injection and sensing. Finally, the effect of BTs on the operation and reliability of high-mobility channel MOSFETs is discussed. It is also shown that the density of BTs is closely linked to the quality or defectivity of the high- k gate stack, indicating room for improvement by optimization of processing or by implementation of a suitable bulk-oxide defect passivation step.

(Invited) Non Planar Non Si CMOS - Challenges and Opportunities

High mobility materials (such as SiGe, Ge and III-V) are attractive replacements for the conventional Si channel material in future CMOS technology nodes (<11nm) to improve performance and reduce power. To control short channel effects at these aggressively scaled device geometries, non-planar multi-gate devices will be needed. Although progress has been made in high mobility non-planar devices with SiGe, Ge and III-V channel materials, significant integration challenges remain. In this paper, the opportunities of non-planar non-Si CMOS and the hetero-integration challenges of high mobility material epitaxy on Si are discussed.

MOSCAP's and MOSFET's on III-V Channel Materials with Si, Ge and SiGe Interface Passivation Layer

The electrical characteristics of TaN/HfO2/GaAs MOS capacitors with various interface passivation layers (Si, Ge and SiGe IPLs) under various PDA (post-deposition anneal), PMA (post-metal anneals) and process conditions are presented. High-k GaAs MOSFETs with reasonable electrical characteristics (i.e. thin EOT (< 2nm), low frequency dispersion (<5%) and peak mobility (1218 cm2/V-s) have been obtained.

MOSCAP's and MOSFET's on III-V Channel Materials with Si, Ge and SiGe Interface Passivation Layer

not Available.

Nanoscale Transistors: Physics and Materials

ABSTRACTWe analyze a modern-day 65nm MOSFET technology to determine its electrical characteristics and intrinsic ballistic efficiency. Using that information, we then predict the performance of similar devices comprised of different materials, such as high-k gate dielectrics and III-V channel materials. The effects of series resistance are considered. Comparisons are made between the performance of these hypothetical devices and future generations of devices from the ITRS roadmap, including double-gate MOSFETs. We conclude that a Si channel device with a high-k gate dielectric and metal gate will outperform III-V channel materials for conventional CMOS applications, but will still not suffice in achieving long-term ITRS goals.