IC Pins Research Articles

An In-Circuit Test Method for Measuring the Bonding Resistances of Individual IC Pins From an Interconnected Multiple IC Assembly of Flexible Hybrid Electronics

An in-circuit test method for extracting the series parasitic resistance associated with the bonding material used to attach IC chips to Flexible Hybrid Electronic assemblies is presented. The method exploits the on-chip electro-static-discharge (ESD) protection circuits of commercial ICs during the measurement and utilizes analog guarding for isolating the measurement path. This approach obviates the need for accessing the terminals of the IC, as these are difficult to access in a Flexible Hybrid Electronic Assembly. Experiments with proposed approach reveals resistance measurement from 10 m <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> to <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$300~\Omega $ </tex-math></inline-formula> within 10 kHz bandwidth with less than 5% error, while lower limit of the resistance across the applied analog guard is ~20 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text{m}\Omega $ </tex-math></inline-formula> . The proposed method is applied to a multi-IC assembly of Flexible Hybrid Electronics subjected to cyclic bending and the experimental results are presented.

An improved test methodology for detecting one-case latent damage in inverter circuit under ESD pulses

Latent damage in IC chips with packaging is becoming one of the major concerns for industry nowadays. In this work, a transmission line pulse (TLP) method is used to analyze the lower ESD pulses that can cause one-case latent damage rather than hard failure in the chip. A new voltage distribution strategy for one of the pins of a packaged IC is proposed to reflect the latent damage caused by ESD stress. The impact of the latent damage can be evaluated through leakage current and low frequency noise (LFN) measurements. It is observed that LFN is more sensitive for detecting the latent damage than leakage current when the IC pin is subjected to a lower TLP voltage. Experimental results show that LFN density changes dramatically when the number of ESD pulses and TLP voltage increases. Therefore, using TLP plus LFN measurement provides a more sensitive test methodology for detecting latent damage of IC chip under ESD pulses. For future ICs design, it is possible to predict the latent damage of ICs and screen out low quality and poor reliability ICs based on this improved test methodology.

The role of ICP in traumatic brain injury

THE ROLE OF ICP IN TRAUMATIC BRAIN INJURY Traumatic brain injury is a major problem in the current life style including motor vehicle accidents, fall from height, industrial injuries & assault cases. The current treatment of severe traumatic brain injury (GCS < 8) will include intubation, assisted ventilation, removal of intracranial hematomas, decompression craniotomy & all these interventions are assisted & guided by proper intra cranial pressure monitoring. The types & the role of ICP in management of traumatic brain injury will be discussed in addition to the most up to date research on the topic will be discussed in my presentation.

IC Pin Modeling and Mitigation of ESD-Induced Soft Failures

In this article, electrostatic discharge (ESD) induced soft failures (SFs) of a USB3 Gen1 device are investigated by direct transmission line pulse injection with varying pulsewidth, amplitude, and polarity to characterize the failure behavior of the interface and to create a SPICE model of the voltage and current waveform dependent failure thresholds. ESD protection by transient-voltage-suppression diodes is numerically simulated in several configurations. The results show viability of using well-established hard failure mitigation techniques for improving SF robustness. A good agreement between numerical simulation for optimized board design and measurements are achieved. A novel concept of SF system efficient ESD design is proposed and demonstrated to be effective for making decisions during early product development, in board designing and prototyping phase.

Susceptibility of Operational Amplifiers to Conducted EMI Injected Through the Ground Plane into Their Output Terminal

In practical printed circuit board (PCB) designs, electromagnetic interference (EMI) is coupled from the ground plane, which is commonly shared among the analog, digital, and mixed-signal integrated circuits. This noisy ground plane couples interference capacitively to all the IC pins, including the output: this effect is exacerbated when the IC is connected to long wires and traces that are routed close to the conductive ground plane. This paper reports on the effect of interference, which is coupled capacitively from the PCB ground plane into all the IC pins of an opamp connected as a voltage buffer. Simulations illustrate the susceptibilities in custom operational amplifier designs, and are corroborated by measurements on several commercial devices. These measurements show that the EMI-induced offset can attain considerable values for the most critical EMI frequencies, which lie between 10 and 100 MHz. Moreover, these illustrate that there is a considerable susceptibility of operational amplifiers to electromagnetic interference coupled to their output pins.

Simulation of ESD Thermal Failures and Protection Strategies on System Level

In this paper, approaches for the modeling and simulation of thermal destruction of ICs due to ESD are discussed from a system point of view. Considered systems consist of ESD generator, PCB, protection element, and IC. A direct connection between the ESD generator and the system is always assumed. For the modeling of an IC ESD destruction, the electric behavior model of an IC pin to ground or supply is extended with a thermal destruction model. The thermal model consists mainly of a thermal resistance and a thermal capacitance. When structure temperature reaches a threshold, a failure is assumed. All needed model parameters can be found with a set of measurements and tests. No internal knowledge of the IC or protection element structures is required. The methodology was applied to several ICs, protection elements, and system structures with emphasis on automotive electronics. All needed component model parameters were generated from measurements. Models and parameter measurements are described. Results from the system simulation were compared to system test results with hardware. In most cases, the simulation could predict well the destruction behavior of a system. Thermal failure and safe operating area prediction quality are compared. The described simulation method helps with selection of protection strategies and optimization of system ESD robustness.

Feature-Based Object Location of IC Pins by Using Fast Run Length Encoding BLOB Analysis

Feature-Based Object Location of IC Pins by Using Fast Run Length Encoding BLOB Analysis

Design of current-mode modular programmable analog CMOS FLC

One of the active areas of fuzzy logic applications is control systems. In this paper presents a proposed Fuzzy Logic Controller FLC chip utilized a novel Membership Function Circuit MFC which can be made programmable. This membership function features of large dynamic range, high current driving, high noise immunity and is simply tunable by setting some voltages on IC pins. Each input of controller has five membership functions and output has seven singletons. A new structure for Min/Max operators, and also, a new current-mode divider circuit with very small area, very low power consumption and high speed and accurate are presented, which are compatible to the proposed MFC, are also given. This controller is a general-purpose two-input one-output fuzzy controller that can be implemented in 0.08-mm2 in 0.35-μm CMOS technology BSIM3v3. For general control tasks, input-output inference of FLC is voltage/voltage. The maximum delay in output of FLC is about 67-ns that correspond to 15-MFLIPS Fuzzy Logic Inference per Second and power consumption is 2.5-mW.

Contactless Test of IC Pads, Pins, and TSVs via Standard Boundary Scan

The performance of an IC's inputs and outputs (I/Os) is always specified in IC data sheets and is the performance most likely to be affected by assembly steps. As the speed and number of I/Os increase beyond low-cost ATE capabilities, and I/O pads become smaller (less than 10 microns wide for 3D assemblies), built-in self-test (BIST) of this performance becomes more attractive. This article describes a BIST that exploits relatively low-speed IEEE 1149.1 boundary scan to access the I/Os and test performance with as low as 5 ps calibrated resolution, equivalent to a bandwidth approaching 100 GHz.

Electrostatic Discharge Effects in Ultrathin Gate Oxide MOSFETs

The effects of destructive and nondestructive electrostatic discharge (ESD) events applied either to the gate or drain terminal of MOSFETs with ultrathin gate oxide, emulating the occurrence of an ESD event at the input or output IC pins, respectively, were investigated. The authors studied how ESD may affect MOSFET reliability in terms of time-to-breakdown (TTBD) of the gate oxide and degradation of the transistor electrical characteristics under subsequent electrical stresses. The main results of this paper demonstrate that ESD stresses may modify the MOSFET current driving capability immediately after stress and during subsequent accelerated stresses but do not affect the TTBD distributions. The damage introduced by ESD in MOSFETs increases when the gate oxide thickness is reduced.

Experimental evaluation of error-detection mechanisms

Effective error-detection is paramount for building highly dependable computing systems. A new methodology, based on physical and simulated fault injection, has been developed for assessing the effectiveness of error-detection mechanisms. This approach has 2 steps: (1) transient faults are physically injected at the IC pin level of a prototype, in order to derive the error-detection coverage. Experiments are carried out in a 3-dimensional space of events. Fault location, time of occurrence, and duration of the injected fault are the dimensions of this space. (2) Simulated fault-injection is performed to assess the effectiveness of new error-detection mechanisms, designed to improve the detection coverage. Complex circuitry, based on checking for protocol violations, is considered. A temporal model of the protocol checker is used, and transient faults are injected in signal traces captured from the prototype system. These traces are used as inputs of the simulation engine. s-confidence intervals of the error-detection coverage are derived, both for the initial design and the new detection mechanism. Physical fault-injection, carried out on a prototype server, proved that several signals were sensitive to transient faults and error-detection coverage was unacceptably low. Simulated fault injection shows that an error-detection mechanism, based on checking for protocol violations, can appreciably increase the detection coverage, especially for transient faults longer that 200 nanoseconds. Additional research is required for improving the error-detection of shorter transients. Fault injection experiments also show that error-detection coverage is a function of fault duration: the shorter the transient fault, the lower the coverage. As a consequence, injecting faults that have a unique, predefined duration, as it was frequently done in the past, does not provide accurate information on the effectiveness of the error-detection mechanisms. Injecting only permanent faults leads to unrealistically high estimates of the coverage. These experiments prove that combined physical and simulated fault injection, performed in a 3-dimensional space of events, is a superior approach, which allows the designers to accurately assess the efficacy of various candidate error-detection mechanisms without building expensive test circuits.

ＬＳＩ用Ａｌパッドに対するジンケート前処理のシミュレーション実験

Small Al electrodes connected to the pins of a model IC were subjected to zincate pretreatment to simulate the plating process in an LSI manufacturing line. From SEM observation, deposition of Zn and dissolution of Al substrate depended on the potential of Al electrodes under the potentiostatic polarization in the zincate solution. Difference in electric impedance of IC pins affected the immersion potenial of Al electrodes in the zincate solution and thus the amount of Zn deposition. Visible light illumination on the separated p-Si electrode additionally connected to the power supply pin of the IC generated photocurrent. This caused a shift in immersion potential of Al electrodes connected to the other pins of the IC in a noble direction, resulting in suppression of Zn deposition in the zincate pretreatment.

Design of an analog CMOS fuzzy logic controller chip

We propose an analog fuzzy logic controller chip structure in 1.2 μm CMOS technology. It employs a new architecture for fuzzifier circuit that generates membership functions with a very suitable range and precision. These membership functions are simply tunable by setting some voltages on IC pins. Input has three membership functions and output is five singleton membership functions. Also, a novel defuzzifier circuit is used which occupies a small chip area. The controller is tested for two inputs, one output, and nine tunable fuzzy rules. The proposed architecture has an operation speed of 6.25 MFLIPS (6.25×10 6 fuzzy logic inference per second) and power consumption of 16.3 mW . The whole chip area is less than 0.7 mm 2 which is very small. Simulation tests show a good functionality of controller in response to some inputs to confirm the success of the design. The application of the system to the synthesis of a second-order system in a feedback loop is also considered.

Enhanced Reduced Pin-Count Test for Full-Scan Design

This paper presents enhanced reduced pin-count test (E-RPCT) for low-cost test. E-RPCT is an extension of traditional RPCT for circuits in which a large number of digital IC pins is multiplexed for scan. The basic concept of E-RPCT is to provide access to the internal scan chains via an IEEE 1149.1 compatible boundary-scan architecture, instead of direct access via the IC pins. The boundary-scan chain performs serial/parallel conversion of test data. E-RPCT also provides I/O wrap to test non-contacted pins. The paper presents E-RPCT for full-scan design, as well as for full-scan core-based design.

Teraflops supercomputer: architecture and validation of the fault tolerance mechanisms

Intel Corporation developed the Teraflops supercomputer for the US Department of Energy (DOE) as part of the Accelerated Strategic Computing Initiative (ASCI). This is the most powerful computing machine available today, performing over two trillion floating point operations per second with the aid of more than 9,000 Intel processors. The Teraflops machine employs complex hardware and software fault/error handling mechanisms for complying with DOE's reliability requirements. This paper gives a brief description of the system architecture and presents the validation of the fault tolerance mechanisms. Physical fault injection at the IC pin level was used for validation purposes. An original approach was developed for assessing signal sensitivity to transient faults and the effectiveness of the fault/error handling mechanisms. Dependency between fault/error detection coverage and fault duration was also determined. Fault injection experiments unveiled several malfunctions at the hardware, firmware, and software levels. The supercomputer performed according to the DOE requirements after corrective actions were implemented. The fault injection approach presented in this paper can be used for validation of any fault-tolerant or highly available computing system.

Nanometer technology challenges for test and test equipment

Designers can now place millions of transistors on a single chip and propagate a signal through them at speeds approaching one gigahertz. With all this progress on the design front, it's easy to overlook a simple fact: more complex designs also pose problems for manufacturing and test. The challenges are especially acute in test. Test costs traditionally rise as frequency, transistors, and pin counts increase. Without substantial changes in test technology, the billion-transistor ICs projected within the next 12 years could cost many times more to test than the 40-million-transistor microprocessors of today. Test costs today are already high. Current IC pin counts are in the hundreds. Nanometer designs are anticipated to have pin counts in the thousands. Manufacturers will continue to pay these high test-equipment costs far some time because the cost of changing systems is even more staggering. Why are these costs so high and how are they affected by nanometer technologies? The author answers these questions by looking to the defects that occur in semiconductor manufacturing.

An advanced 5 V VIF/SIF PLL for signal detection in TV sets and VTRs

The authors describe the design of a bipolar analog 5-V IC which contains a phase-locked loop (PLL) for vision and sound IF signal processing in TV sets and video tape recorders. The IC incorporates one PLL for demodulating the vision IF signal and another PLL for demodulating the FM sound IF signal. All the stages for signal amplification, gain control, and limiting and the two PLLs are on a single chip. This high level of integration, achieved with the advanced 5-V circuit and modern high-frequency IC technology, has considerably reduced the number of IC pins, external components, and alignment. Excellent video and intercarrier sound performance have been observed, and the design consumes only 300 mW of power.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Video camera signal processing IC with CCD delay lines

A video camera signal-processing IC that includes CCD (charge coupled device) delay lines (DLs) and lowpass filters has been developed using a Bi-CMOS/CCD process. The IC greatly contributes to reduced size and improved reliability in video movie circuits. The IC incorporates four 1H CCD-DLs and five lowpass filters, thereby making the circuit board space more compact. Automatic adjustment of CCD-DL output signal level, DC bias, and lowpass filter cutoff frequency greatly reduces adjustment points and IC pins. >

Computer Simulation of Pulse Propagation Through a Periodic Loaded Transmission Line

In view of the speed of today's hardware components, wirings between IC pins cannot be regarded as ``short circuit jumper+some C'' but should be treated as a piece of transmission line. The central problem in design of any equipment employing a number of IC is thus to predict the extent of gradual deterioration of waveforms as pulses propagate along a length of transmission line loaded with many lumped constant loads at distances. A simulation technique for this problem is introduced in the paper, and the technique is more practical than those previously described.