An improved test methodology for detecting one-case latent damage in inverter circuit under ESD pulses

Abstract

Latent damage in IC chips with packaging is becoming one of the major concerns for industry nowadays. In this work, a transmission line pulse (TLP) method is used to analyze the lower ESD pulses that can cause one-case latent damage rather than hard failure in the chip. A new voltage distribution strategy for one of the pins of a packaged IC is proposed to reflect the latent damage caused by ESD stress. The impact of the latent damage can be evaluated through leakage current and low frequency noise (LFN) measurements. It is observed that LFN is more sensitive for detecting the latent damage than leakage current when the IC pin is subjected to a lower TLP voltage. Experimental results show that LFN density changes dramatically when the number of ESD pulses and TLP voltage increases. Therefore, using TLP plus LFN measurement provides a more sensitive test methodology for detecting latent damage of IC chip under ESD pulses. For future ICs design, it is possible to predict the latent damage of ICs and screen out low quality and poor reliability ICs based on this improved test methodology.