IC Integration Research Articles

Low-temperature Cu-Cu direct bonding with ultra-large grains using highly (110)-oriented nanotwinned copper

With the application of Cu-Cu direct bonding technology in high-performance electronic devices, improving bonding reliability is essential for achieving high-density 3D IC integration. In this study, we innovatively applied highly (110)-oriented perpendicular nanotwinned Cu (p-ntCu) to achieve Cu-Cu direct bonding at low temperature and pressure. The anisotropic growth of p-ntCu during annealing at 200 °C resulted in the formation of ultra-large grains, which could improve the conductivity of the electrodeposited Cu film. Two Cu films were bonded at 200–250 °C with 2 MPa pressure for 1 h, and there was almost no void at the bonding interface. Anisotropic grain growth occurred within the bonding joint and grain boundary migration was observed at the bonding interface. The shear strength after bonding at 250 °C was measured as 58.3 MPa on average, indicating a relatively high quality of such Cu-Cu bonding. The p-ntCu can achieve Cu-Cu bonding and improve the conductivity by anisotropic grain growth at low temperature and pressure, which has great potential for Cu interconnect applications.

Impact of magnetic field variation on thermally annealed tantalum-filled vertical superconducting interconnects for scalable quantum computing systems

Efforts to scale down advanced quantum processors with more numbers of qubits offer challenges since the integration of qubits is a significant obstacle in the path. Superconducting vertical interconnects in 3D IC integration can provide a crucial solution for wiring complexities, as shorter interconnections reduce energy loss when working in cryogenic conditions with better signal fidelity. Using the time-dependent Ginzburg–Landau equation, this simulation study analyzes vertical superconducting interconnects filled with materials like tantalum, niobium, and thermally annealed tantalum. It also investigates how London penetration depth (temperature-dependent) and magnetic fields affect Cooper pair density and, consequently, current density.

Innovations in Intracoronary Imaging: Present Clinical Practices and Future Outlooks.

Engaging intracoronary imaging (IC) techniques such as intravascular ultrasound or optical coherence tomography enables the precise description of vessel architecture. These imaging modalities have well-established roles in providing guidance and optimizing percutaneous coronary intervention (PCI) outcomes. Furthermore, IC is increasingly recognized for its diagnostic capabilities, as it has the unique capacity to reveal vessel wall characteristics that may not be apparent through angiography alone. This manuscript thoroughly reviews the contemporary landscape of IC in clinical practice. Focused on current methodologies, the review explores the utility and advancements in IC techniques. Emphasizing their role in clarifying coronary pathophysiology, guiding PCI, and optimizing patient outcomes, the manuscript critically evaluates the strengths and limitations of each modality. Additionally, the integration of IC into routine clinical workflows and its impact on decision-making processes are discussed. By synthesizing the latest evidence, this review provides valuable insights for clinicians, researchers, and healthcare professionals involved in the dynamic field of interventional cardiology.

Co-Packaged Optics - Heterogeneous Integration of Photonic IC and Electronic IC

Abstract The trends in co-packaged optics will be investigated in this study. Emphasis is placed on the heterogeneous integration of photonic IC (PIC) and electronic IC (EIC). In particular, 2D and 3D heterogeneous integration of ASIC Switch, PIC and EIC w/o bridges, and heterogeneous integration of ASIC Switch, PIC and EIC on glass substrate will be discussed. Some recommendations will be provided.

Non-Contact Integration of Photonic IC and Electronic IC via Inductively Coupled Interconnects

Non-Contact Integration of Photonic IC and Electronic IC via Inductively Coupled Interconnects

Microstructural effects of copper deposits on direct bonding for 3D IC integration

Cu-to-Cu direct bonding has been regarded as an important approach to achieve three-dimensional integrated circuit integration. This study aims to investigate the effects of microstructure and Xenon flash exposure on the direct bonding of copper deposits. Copper electrodeposits, along with a sputtered deposit, with various grain sizes, preferred orientations, as well as surface hardnesses, were prepared to clarify the influence of individual factors quantitatively. Experimental results show that joint strength and grain boundary density followed a positively linear relationship regardless of other microstructural differences, suggesting the dominating role of grain boundary diffusion. Grain refinement can effectively enhance bonding strength, even only one side of the directly bonded joints possessed fine grains. Considering the portable device applications which may suffer from drop shocks, drop testing of the packages comprising sputtered copper on Si chips joined with electroplated copper on Al2O3 substrates assembled by thermal compression bonding was performed for the first time. Noticeably, a proper flash irradiaiton prior to bonding brought about not only remarkable improvement in shear strength by up to 60 % but also drop resistance for direct-copper bonds. The resistance against drop shock for directly-bonded daisy chains subjected to an appropriate light exposure prior to bonding was superior than the joints bonded using impact-resistant solders.

Study on Single-Phase BLDC Motor Design through Drive IC Integration Analysis

In this paper, a single-phase BLDC motor is applied to a cooling fan motor and a Drive IC integration analysis method of the single-phase BLDC motor is proposed. Single-phase BLDC motors have a simple structure, are easy to manufacture, and are low cost, so they are used in applications where low outputs and low costs are advantageous. Single-phase BLDC motors use a full-bridge inverter (Drive IC), and this inverter (Drive IC) has dead time due to switching. Therefore, in order to consider dead time when analyzing a single-phase BLDC motor, analysis through integration with Drive IC is necessary. This paper compares the types of single-phase BLDC motors, designs a model that satisfies target performance, and conducts research on Drive IC integration analysis through FEA. A prototype motor was manufactured and tested, and the validity of the Drive IC integration analysis was verified.

Single-Crystal Germanium by Elevated-Laser-Liquid-Phase-Epitaxy (ELLPE) Technique for Monolithic 3D ICs

This paper proposes and demonstrates single-crystal Germanium (Ge) growth by elevated-laser-liquid-phase-epitaxy (ELLPE) and the fabrication of Ge Fin field-effect transistors (FinFETs) for the monolithic three-dimensional integrated circuits (monolithic 3D ICs). This technique permitted the fabrication of single-crystalline (100) Ge film and FinFETs without random grain boundaries. In comparison with the poly-Ge FinFETs, the ELLPE Ge FinFETs exhibit superior performance and uniformity. Moreover, the ANSYS simulated maximum temperature of bottom circuits during the ELLPE technique does not exceed 400°C, therefore allowing monolithic 3D integration of ICs.

State-of-the-Art and Outlooks for 2.3D IC Integration

The state-of-the-art and outlooks for 2.3D IC integration will be investigated in this study. Emphasis is placed on the design, materials, process, advantages and disadvantages, challenges (opportunities), and examples of 2.3D IC integration for chiplet design and heterogeneous integration packaging. Also, some recommendations of 2.3D IC integration will be presented.

Fluctuation analysis and experimental evaluation of an inductor-less battery charge equalization circuit with a CMOS cross-coupled structure

A lithium-ion battery for mobile devices obtains a desired voltage by connecting a plurality of battery cells in series. However, the variation in the voltage of each battery cell shortens the lifetime of the battery. For this reason, a battery charge equalization circuit called a battery equalizer (BE) is commonly used. Among others, an inductor-less switched-capacitor (SC) BE is one of the most promising circuits, because it enables low cost, easy control, low EMI, and IC integration. However, to the best of our knowledge, there has been no research on the effects of element variation in inductor-less SCBEs. In this paper, the effect of circuit element variation is investigated regarding the inductor-less SCBE. Specifically, we use Monte-Carlo simulations to clarify the effects of circuit element variation in an inductor-less SCBE with a CMOS cross-coupled structure. Furthermore, the feasibility of the inductor-less SCBE is confirmed by experiments on a laboratory prototype circuit.

Electronically Tunable Current Mode Instrumentation Amplifier Employing Single DV-EXCCCII

In this paper, a new design of a current mode instrumentation amplifier (CMIA) is presented using a single differential voltage extra-X current controlled current conveyor (DV-EXCCCII) and a grounded resistor. Therefore, this circuit design is very simple and suitable for IC integration. The proposed circuit of instrumentation amplifier has high output impedance so it is easily cascadable with other current mode circuits without buffer requirement. Furthermore, the proposed circuit is electronically tunable with the bias current of the active element used. This circuit offers good frequency performance with wide differential gain and CMRR bandwidth. The non-idealities and parasitic effects of the proposed circuit are also investigated. To validate the proposed instrumentation amplifier, various simulations are performed using the CADENCE VIRTUOSO SPECTRE simulator using 0.18 µm CMOS technology parameters.

High-Speed Dicing of SiC Wafers with 0.048 mm Diamond Blades via Rolling-Slitting.

In this study, an innovative fabrication method called rolling-slitting forming, which forms ultra-thin diamond blades, was presented for the first time. Furthermore, the feasibility of the rolling-slitting forming method when applied to silicon carbide wafer dicing blades was investigated; moreover, the cold-pressing blade samples were manufactured through the conventional process under the same sintering conditions to compare and analyze the manufacturing efficiency, organization and performance. The results show that the new method achieves high-precision and low-thickness dicing blades through continuous production without molds-with the thinnest blades being 0.048 mm thick. Furthermore, the rolling-slitting blade has a unique multiporous heat-conductive matrix structure and in-situ generated amorphous pyrolytic carbon, which can reduce the dicing resistance and contribute to a better cutting quality. In addition, the effects of the dicing parameters on SiC were investigated by using indications of spindle current, dicing chipping size and kerf width during the high dicing process. For a dicing depth of 0.2 mm, the ideal performance of dicing SiC with an ultra-thin blade was achieved at a spindle speed of 22,000 rpm and a feed rate of 5 mm/s. This research provides a new idea for the manufacturing of dicing blades, which can satisfy the demand for ultra-narrow dicing streets of high integration of ICs.

Design of high reliability LDO regulator with NLRSCR based ESD protection circuit using dynamic feedback loop for low-voltage applications

Capacitor-less low dropout voltage regulator applied to the mobile devices consistently exposes the peak voltage, which can increase the power consumption. This study proposes a dynamic feedback loop of the LDO regulator that provides a function to stably control the peak voltage irrespective of the change of the load current. The performance of the chip layout was evaluated under conditions of an output voltage of 3 V, a battery input voltage of 3.3 to 4.5 V, and a load current of 350 mA. As a result, the peak voltage keeps an undershoot voltage of 30 mV and an overshoot of 33 mV along the load current. In addition, the demand for miniaturization and integration of ICs and the application of low voltage applications are increasing. Thereby, the circuit damage due to ESD (Electro Static Discharge) may happen frequently. This is a significant factor influencing the overall reliability related to productivity and stability. In this study, we confirmed that the proposed LDO regulator with the ESD protection circuit of the NLRSCR structure secures high reliability at low voltage.

(Invited) 3DIC Hierarchical Thermal and Mechanical Analysis with Continuum and Atomistic Modeling

3D IC heterogeneous integration technologies employ numerous materials with widely varying thermal and mechanical properties and distinct deformation behaviors. During 3D integration processes, the constituent materials undergo various thermal cycles. Because of thermal expansion coefficient mismatch, the materials are essentially subject to mechanical loadings for these thermal ramps. The resulting chip, package, and board interactions lead to 3D stack warpage, silicon mobility variation, and material damage. Under operation conditions, heat can be trapped between insulation layers and leads to nonuniform temperature rises. Elevated local temperatures can change carrier mobility, relax mechanical stress, and affect material deformation behaviors. Consequently, these local temperature rises can affect device performance, structure integrity, and material reliability. To accurately assess these thermal and mechanical effects, extract design rules, optimize designs, and develop performance and reliability mitigation methodologies, it is of paramount importance to characterize material deformation and interface de-bonding behaviors, map chip temperature distributions, and analyze stress hotspot evolutions during integration process and under operation conditions while developing 3D IC integration technologies [1].In this study, a multiscale hierarchical modeling approach is assembled to analyze thermal, mechanical, and material deformation and interface de-bonding behaviors under 3D integration process and operation conditions for a newly designed 3D IC package with a 2nm SOC die copper-bonded on an RDL interposer [2]. The 3DIC structures are constructed directly using GDSII design and ITF technology data [3]. Each structural layer is divided into small smear tiles. Each tile is represented by anisotropic thermal and mechanical properties that depend on local feature patterns in the tile. Under given operation conditions, power grids are generated and used as heat sources for thermal analysis. For multiscale hierarchical modeling, the global thermal and mechanical analyses that call for coarse grain resolution are first performed. The subsequent local analyses that provide fine grain resolution in areas of interests utilize boundary conditions that are extracted from the global analyses. The material deformation and interface de-bonding behaviors are simulated using molecular dynamics [4]. Several 3D integration design options are explored. The 3D configuration effects on chip temperature distributions during operations, stack warpages, silicon mobility variations, and chip package interaction induced stress hotspots are examined. The elevated temperature impacts on material deformation and de-bonding process are also investigated.

(Invited) Tutorial on Semiconductor Advanced Packaging

In this lecture semiconductor advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance and are grouped into 2D, 2.1D, 2.3D, 2.5D, and 3D IC integration, which will be presented and discussed. Key enabling technologies such as flip chip and fan-out will be briefly mentioned. The trends and challenges (opportunities) of advanced packaging will be discussed. Also, in this lecture, chiplet design and heterogeneous integration packaging are defined. The chiplet design and heterogeneous integration packaging such as those given by Xilinx, AMD, Intel, TSMC, and Samsung will be presented and discussed. The lateral communication between chiplets such as the silicon bridges embedded in organic build-up package substrate (Intel’s EMIB and IBM’s DBHi) and fan-out epoxy molding compound (Applied Materials’ chip-first face-up, Unimicron’s chip-first face-down, TSMC’s LSI, SPIL’s FO-EB, ASE’s sFOCoS, IME’s EFI, and Amkor’s S-Connect Fan-Out Interposer) as well as flexible bridges will be presented. Key enabling technologies such as thermocompression bonding and hybrid bonding will be briefly mentioned. The trends and challenges (opportunities) of chiplet design and heterogeneous integration packaging will be discussed.

Recent Advances and Trends in Multiple System and Heterogeneous Integration With TSV-Less Interposers

In this study, the recent advances and trends in multiple system and heterogeneous integration with through-silicon via (TSV)-less interposer (organic interposer or 2.3-D IC integration) will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of multiple system and heterogeneous integration with TSV-less interposer. Also, some recommendations of 2.3-D IC integration will be provided.

Automatic detection method for BGA defects based on x-ray imaging.

Ball grid array (BGA) packaging is a high-density surface mount technology with the advantages of small size, good heat dissipation, and electrical properties, and is widely applied in the production of large-scale integrated circuits. With the rapid development of IC integration, devices assembled using BGA technology generally have greater complexity. However, BGA defects can seriously affect device performance and bring difficulties to product quality inspection. More importantly, in the process of BGA defect inspection, the high complexity of the device brings unprecedented challenges to the precise location of defects, which means that corresponding inspection methods should be improved. To this end, this paper proposes an automatic detection method for BGA defects based on x-ray imaging. First, x-ray imaging technology is utilized to achieve non-destructive detection of the BGA area inside the device and generate image data. On this basis, a set of algorithms including threshold separation, detection filling, and closing operation is designed to complete automatic detection of BGA defects. Furthermore, to objectively evaluate the effectiveness and performance of the proposed method, we conduct a series of comparative experiments using simulated and real data, and generate visual outputs. Through these experiments and analyses, we confirm that the proposed method plays an active and effective role and has robust performance in BGA defect detection. In particular, our method shows the expected performance in precisely finding BGA edge defects and subtle defects.

New Heuristic Algorithm for Low Energy Mapping for 2.5-D Integration

A chiplet placement algorithm for 2.5-D IC integration on an interposer is discussed in this paper. Inspired by the NoC (network-on-chip) mapping problem, we propose a novel chiplet placement algorithm called the CCEOA (chiplet communication energy optimization algorithm), which takes into account the actual size of the chiplet. The CCEOA can map chiplets to mesh topology, resulting in a layout with a low CEC (communication energy consumption). The algorithm considers the spacing of the chiplets while selecting the initial nodes and the nodes to map the next chiplet. Furthermore, because there exist nodes resulting in the same CEC increment during the mapping process, the algorithm adopts a secondary local exploration strategy to further select nodes. Meanwhile, the lateral and vertical placements of chiplets are also considered. The algorithm is implemented and evaluated with a 2.5-D IC integration with 22 chiplets to demonstrate its efficiency and the accuracy.

Recent Advances and Trends in Advanced Packaging

In this study, advanced packaging is defined. The kinds of advanced packaging are ranked based on their interconnect density and electrical performance, and are grouped into 2-D, 2.1-D, 2.3-D, 2.5-D, and 3-D IC integration, which will be presented and discussed. Chiplet design and heterogeneous integration packaging provide alternatives to the system on chips (especially for advanced nodes) will be discussed. Different substrates, such as size, pin-count, and metal linewidth and spacing for advanced packaging, are examined. The lateral communication between chiplets, such as the silicon bridges embedded in organic build-up package substrate and fan-out epoxy molding compound, as well as flexible bridges, will be presented. Fan-in packaging, such as the six-side molded wafer-level chip-scale package (WLCSP) and its comparison with the ordinary WLCSP, are presented. Fan-out packaging, such as the chip-first with die face-up, chip-first with die face-down, and chip-last and their difference, will be provided. Low-loss dielectric materials for high-speed and high-frequency applications in advanced packaging will be presented. Flip-chip assembly by mass reflow, thermocompression bonding, and bumpless hybrid bonding will be briefly mentioned first.

Single EX-CCCII based electronically tunable current mode instrumentation amplifier

The purpose of this study is to present a new design for an electronically tunable instrumentation amplifier. The current-mode design approach is used for the proposed circuit. The proposed current-mode instrumentation amplifier employs a single Extra-X Current Controlled Current Conveyor (EX-CCCII) and a grounded resistor. This circuit design is very simple and suitable for IC integration. Because of the circuit's high output impedance, it can be cascaded with other current-mode circuits without the need for a buffer. In addition, this circuit is electronically tunable with the bias current from EX-CCCII. The proposed instrumentation amplifier provides good frequency performance with a wide bandwidth for differential gain and CMRR. The effects of non-idealities of EX-CCCII and its parasitic elements are also analysed. To validate the proposed instrumentation amplifier, various simulations are performed with the CADENCE VIRTUOSO SPECTRE simulator using 0.18 µm CMOS technology parameters.