Networks-on-Chip (NoC) is an impending research area for designing future System-on-Chip (SoC). NoC futures are allied with intellectual property (IP) reusability, parallel communication within IPs and scalability against standard interconnection NoC topology. In this paper, we introduce a new hybrid topology namely Four Regular Dense Spidergon (FRDS) based deterministic NoC architecture with 64 cores. We propose cluster and generic heuristic based approach For mapping of applications onto FRDS topology. Genetic algorithm (GA) + simulated annealing (SA) have been considered under generic heuristic approach for successful mapping of core into topology and fair comparison of the performance of the proposed FRDS. Under normalized condition with respect to Mesh, experimental findings of proposed FRDS against real benchmark traces provide an average improvement on execution time with 1.20% and 4.81% over DMesh and ZMesh. Further, an average improvement on energy consumption was obtained 8.13% and 5.35% over DMesh and ZMesh. We adopt constant geometric traffic and the synthetic traffic pattern to measure the performance of proposed FRDS. The experimental results clearly indicates an improvement in power latency product under geometric traffic by 16.27% and 12.23% over DMesh and ZMesh. Similarly under synthetic traffic pattern, the proposed FRDS offers an improvement up to 22.51% and 45.53% over DMesh and ZMesh respectively. To realize the effectiveness of the link usage, brief evaluation of link utilization has been carried out with balanced load.