Hybrid Multiplier Research Articles

Optimizing FIR Filter Efficiency with Advanced Hybrid Multiplier Techniques

Optimizing FIR Filter Efficiency with Advanced Hybrid Multiplier Techniques

Optimizing Visual Sensor Node Image Compression for Resource-Constrained Environments

Abstract: An Approximate hybrid multiplier design is proposed to reduce the data-path width of lifting 2-D discrete wavelet transform (DWT) especially for wireless visual sensor node applications. The proposed multiplier design takes multiplier operand of size less by 3 bit and calculates full-width outputs with marginal loss of accuracy, which is significant. The proposed approximate 2-D DWT structure uses data-path DWT levels and produces reconstructed color images higher than the 70-dB peak-signal-to-noise ratio (PSNR). Compared with the existing fractional wavelet transform (FrWT)-based 2D DWT structures, the proposed structure has a smaller data-path width and free from overhead. Compared with the existing parallel structure

Multiplier subsample bootstrap for statistics of time series

Block-based bootstrap, block-based subsampling and multiplier bootstrap are three common nonparametric tools for statistical inference under dependent observations. Combining the ideas of those three, a novel resampling approach, the multiplier subsample bootstrap (MSB), is proposed. Instead of generating a resample from the observations, the MSB imitates the statistic by weighting the block-based subsample statistics with independent standard Gaussian random variables. Given the asymptotic normality of the statistic, the bootstrap validity is established under some mild moment conditions. Involving the idea of MSB, the other resampling approach, the hybrid multiplier subsampling periodogram bootstrap (HMP), is developed for mimicking frequency-domain spectral mean statistics in the paper. A simulation study demonstrates that both the MSB and HMP achieve good performance.

Design of efficient binary multiplier architecture using hybrid compressor with FPGA implementation

In signal processing applications, the multipliers are essential component of arithmetic functional units in many applications, like digital signal processors, image/video processing, Machine Learning, Cryptography and Arithmetic & Logical units (ALU). In recent years, Profuse multipliers are there. In that, Vedic multiplier is one of the high-performance multiplications and it is used to signal/image processing applications. In order to ameliorate the performance of this multiplier further, by proposed a novel multiplier using hybrid compressor. The proposed hybrid compressor-based multiplier is designed and implemented in Field programmable Gate Array (FPGA—spartan 6). The synthesis result shows that the speed of proposed hybrid compressor-based multiplier gets improved as compared to Array multiplier (35.83%), Wallace tree multiplier (34.58%), Vedic Multiplier based on Carry look ahead adder (CLA) (28.49%), Vedic Multiplier based on Ripple carry adder (RCA) (20.65%), Booth Multiplication (21.65%) and Vedic Multiplication based on Han-Carlson Adder (HCA) (20.10%) and Hybrid multiplier using Carry Select Adder (CSELA) (17.81%) and Hybrid Vedic Multiplier (7.15%).

Enhancing FPGA Testing Efficiency: A PRBS-Based Approach for DSP Slices and Multipliers

The multiplication operations are pivotal in (Application-Specific Integrated Circuits) ASICs and Digital Signal Processors (DSPs). The integration of Field-Programmable Gate Arrays (FPGAs) into modern embedded systems, efficient Built-in Self-Tests (BISTs), particularly for complex components like DSP slices, is essential. This paper evaluates Pseudo Random Binary Sequence (PRBS) generators and checkers as BIST tools for high-speed data transfers in FPGAs. The design achieves minimal errors and remarkable efficiency with less than 4% logic utilization within available Look-Up Tables (LUTs). The testing of embedded multipliers in modern FPGAs is analyzed, shedding light on their performance. The analysis includes Built-in Self-Test (BIST), PRBS generator, PRBS checker, and Bit Error Rate (BER), providing insights into FPGA-based testing. This analysis assesses PRBS tools for high-speed FPGA data transfers. A hybrid multiplier design, featuring BIST and PRBS capabilities, notably reduces DSP slice utilization from 16% to 5%. This liberated FPGA resource enhances operational capabilities. The runtime PRBS data control at the block level design exemplifies adaptability in FPGA testing. The findings underscore PRBS-based BIST potential in FPGA testing. The hybrid multiplier not only optimizes FPGA resources but also aligns with dynamic digital system requirements. This research aids FPGA designers and engineers in advanced testing strategies for evolving embedded systems.

Design and Implementation of Hybrid Multiplier for DSP Applications

In recent decades, there has been a consistent reduction in feature sizes in integrated circuit (IC) technology, leading to the need for increased placement of functional circuits on each chip. When it comes to the design of digital circuits, there is a significant focus on hybrid logic. Hybrid logic is highly regarded due to its ability to consume less power while achieving higher efficiency. Hybrid logic circuits have similarities to complementary metal-oxide-semiconductor (CMOS) transistors, yet possess a reduced transistor count while offering enhanced performance and reliability capabilities. This study examines the modeling and implementation hybrid multiplier with of help of hybrid adder. The functionality of adder is determined with the help of hybrid logic producing XOR/XNOR functionalities in single circuit. The proposed hybrid Multiplier, which incorporates a hybrid Adder, has been successfully designed and implemented using CMOS 45nm technology and Mentor Graphics software the hybrid transistor logic multiplier demonstrates a decrease in total delay of 60% compared to CMOS.

FPGA implementation of proficient Vedic multiplier architecture using hybrid carry select adder

ABSTRACT Nowadays, the application of computations and communications is needed for high performance, reduced size and lower power utilisation. The multiply and add functions are one of the frequently used operations in digital signal processing. Various types of multipliers are available in digital Various types of multipliers are available for various Signal processing applications.. Among these multipliers, Vedic multiplier is one of the most optimised multipliers used in a signal processing module. In the existing method, the Vedic multiplier is designed with conventional adders, which is having higher area utilisation, lower speed and higher power consumption. Hence, the modified Vedic multiplier is proposed to improve the speed of multiplication using hybrid technology. The partial products of the proposed multiplication are added using 2 × 2 Vedic multiplier and hybrid carry select adder (binary to excess one converter (BEC), Han-Carlson adder and Multiplexer). The critical path delays of hybrid 4 × 4 Vedic multiplier are the summation of 2 × 2 Vedic multiplier, two full adders, two multiplexers and two BECs for producing the final product. The proposed hybrid Vedic multiplier is operated at high speed with reduced size as compared to the existing multiplier techniques. The proposed hybrid Vedic multiplier is designed and simulated using Verilog HDL and implemented in Spartan 6 field-programmable gate array device. The implementation results showed that the delay of the proposed multiplier gets ameliorated as compared to array multiplication (30.84%), Wallace tree multiplication (29.52%), multiplication based on compressor (23.71%), Vedic multiplication by carry look-ahead adder (22.91%), Vedic multiplication by ripple carry adder (14.45%), revised booth multiplication (15.42%) and Vedic multiplication by Han-Carlson adder with BEC (13.95%) and hybrid multiplier (11.37%).

Area Efficient Approximate 4–2 Compressor and Probability-Based Error Adjustment for Approximate Multiplier

Many multipliers based on approximate compressors have been developed for error-tolerant applications such as image processing to reduce power, but the combination of them has not been fully studied. This paper proposes a novel 4 gate 4-2 approximate compressor which is complementary with other compressors from earlier work and constructs a hybrid multiplier based on the compressors, a constant approximation, and error correction AND gate. According to the simulation results, the proposed hybrid approximate multiplier has excellent accuracy and electrical performance tradeoff and reduces the power-delay-area product (PDAP) by 66% with an MRED of 2.5% when compared to the exact multiplier.

Approximate Lifting 2-D DWT Hardware Design for Image Encoder of Wireless Visual Sensors

In this paper, a novel approximate hybrid multiplier design is proposed to reduce the data-path width of lifting two-dimensional (2-D) discrete wavelet transform (DWT) especially for wireless visual sensor node applications. The proposed multiplier design takes multiplier operand of size less by 3-bit and calculates full-width outputs with marginal loss of accuracy which is significant. A parallel approximate lifting 2-D DWT structure is derived using the proposed multiplier design. The proposed approximate 2-D DWT structure uses data-path width 9 and 11 for first and second DWT levels and produces reconstructed colour images higher than 70dB peak-signal-to-noise ratio (PSNR). Compared with the existing fractional wavelet transform (FrWT)-based 2-D DWT structures, the proposed structure has a smaller data-path width and free from overhead. The proposed structure has equal or marginally higher on-chip memory requirement than the existing FrWT based 2-D DWT structures, but involves a substantially less area-delay product (ADP) and energy per image (EPI). The ADP and EPI reduction is O(10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> ×). Compared with the existing parallel structure based on hybrid approximate radix-4 and radix-8 encoded Booth multiplier, the proposed approximate structure involves nearly 23% less ADP and 22% less EPI and calculates output images with nearly (4 ~ 7)dB higher PSNR.

Efficient Approximate Multiplier Design Based on Hybrid Higher Radix Booth Encoding

Partial products of higher radix are approximated by partial product segmentation. The encoder skips few lower order bits to segment the partial products for approximation. For a particular type of approximation, one can have many options of choosing the higher radix for hybrid encoding. However, the selection of higher radix is the key to obtain an optimal approximate hybrid multiplier design. In this paper, we made an in-depth study on radix-64 and radix-256 encoding for 4-bit and 5-bit approximations. Proposed a two-term radix-64 encoding and three-term radix-256 encoding for 4-bit approximation to calculate partial-products with lowest maximum absolute error (MAE). Further, we have proposed a simple rule to select the higher radix for hybrid encoding to obtain an efficient approximate multiplier design. To demonstrate the usefulness of the selection rule, two hybrid encoding schemes named R4R64 and R4R256 are formulated by combining radix-4 separately with proposed two-term radix-64 and three-term radix-256 encoding schemes. Separate multiplier designs are derived using the proposed hybrid encoding. Comparison result shows that both the proposed approximate multipliers have identical output accuracy, but the multiplier design based on proposed hybrid R4R64 encoding is more hardware efficient than the other. Compared with the existing approximate multiplier based on hybrid R4R256 encoding for word-length 12, the proposed multiplier design based on R4R64 hybrid encoding involves nearly 15% less area-delay product (ADP) and a marginal 4% less power-delay-product (PDP), but calculates output with higher accuracy. The 2-D DCT structure using proposed R4R64 multiplier involves 13% lesser ADP and 14% less energy consumption when compared with the 2-D DCT structure based on existing hybrid R4R256 multiplier design and computes reconstructed images with nearly 10dB higher pick signal-to-noise ratio (PSNR).

FPGA implementation of high performance digital FIR filter design using a hybrid adder and multiplier

ABSTRACT The energetic growth in portable multimedia and mobile communication system has increased the requirement of high-speed signal processing system with compact area and power consumption. Finite impulse response(FIR) filters are broadly used in image, signal, speech and video signal processing, medical electronics, noise filtering, mobile communication and many other fields. The performance of the whole signal processing system with FIR filter depends on the basic building block of multiplier and adders. Hence, the hybrid FIR filter is proposed to improve the speed of the signal processing system using hybrid adder and hybrid multiplier. In this technique, the basic hybrid adder is designed with the help of 2-bit adders, BEC and 4:1 Multiplexer. Also, the hybrid multiplier is designed based on partial products of two consecutive multiplicand bits which are added at same time using Han-Carlson, Weinberger and Ling adder. The proposed FIR filter is functionally verified and synthesised using Xilinx ISE simulator and is implemented in Spartan 6 FPGA boards. The result shows that the delay of FIR filter using the proposed multiplier is improved by 26.51%, 15.59%, 15.83% and 2.79% as compared with CLA, conventional CSA, CSA-BK-BEC and the proposed adder with array multiplier, respectively.

A Novel Design of High-Performance Hybrid Multiplier

In this brief, a novel design of hybrid multiplier is proposed. The hybrid multiplier is a combination of two different types of multipliers. The latest computing systems require low-power, area, and delay multipliers. In this work, we extend a new idea of high-performance hybrid multiplier by using Wallace–Dadda and Vedic multipliers. The addition of partial products is done by dividing them into smaller groups to obtain faster results. The proposed method is illustrated by designing an 8-bit hybrid multiplier in which the partial products are divided into four subgroups. In this analysis, two different multipliers are applied to alternative groups. Finally, the carry look ahead adder (CLA) is used to reduce carry propagation delay in the proposed hybrid multiplier. The proposed hybrid multiplier has been synthesized using the Cadence virtuoso tool using a 45-nm CMOS technology. This hybrid multiplier is faster, consumes less power, and occupies less area as compared to the conventional hybrid multipliers.

High-Speed Hybrid Multiplier Design Using a Hybrid Adder with FPGA Implementation

The major role of electronic devices is providing low power dissipation and high speed with compact area. The speed of electronic devices depends on arithmetic operations. Multiplication is the important arithmetic operation in many VLSI signal processing applications. Hence, a high-speed multiplier is needed to design any signal processing module. Many multipliers are surveyed in the literature. They are Array, Wallace tree, booth, Vedic and Compressor-based multiplier. The speed of these multipliers depends on partial product accumulation. The hybrid parallel adder-based multiplier is proposed to improve the speed of multiplication compared to the existing technique. In this technique the partial products of, two consecutive bits (multiplicands), are added simultaneously with the help of a hybrid adder (Hancarlson, Weinberger and Ling adder). The proposed architecture is synthesized and simulated using Xilinx ISE 12.1 with various FPGA boards. Synthesized report shows that the speed of proposed multiplier (Spartan 6 FPGA implementation) is improved when compared to an Array multiplier (22.14%), Wallace tree multiplier (20.41%), Multiplier using compressor (13.89%), Vedic Multiplier using CLA (13.03%), Vedic Multiplier using RCA (3.54%), Modified Booth multiplier (4.42%) and Vedic Multiplier using HCA with BEC (3.28%).

Gray Encoded Harmonics Power Line Interference Cancelling Structure Using LMS and NLMS Adaptive Algorithms

This paper proposes the implementation of a Gray encoded structure for harmonics power line interference cancelling. The structure uses dedicated hardware architecture for the Least Mean Square (LMS) adaptive filtering algorithm, as well as its normalized version (NLMS). In the used scheme, from a 60Hz reference signal, the algorithms are able to estimate the superior harmonics, using after these results for the cancelling of interferences related to the signal of interest. In this work, the proposed adaptive filtering architectures and the harmonics generator block use a Hybrid encoding in its data buses, which is a compromise between the minimal input dependency presented by the Binary encoding and the low switching characteristic of the Gray encoding. For the Hybrid structures, new Hybrid multipliers were proposed, and the results showed that those multipliers are more efficient than the Binary ones, by presenting less power consumption in some cases. The implemented harmonic cancelling structure with the LMS and NLMS adaptive filtering architectures were validated and compared by using both Binary and Hybrid encoding. The efficiency of the implemented Hybrid structure for the cancelling of interferences was proved by reducing more power than the Binary one. By the results, we conclude that it could be practicable to implement a harmonic cancelling structure, based on LMS and NLMS adaptive filtering, operating on Hybrid encoding.

Fast Hybrid Karatsuba Multiplier for Type II Pentanomials

We continue the study of Mastrovito form of Karatsuba (MK) multipliers under the shifted polynomial basis (SPB). An MK multiplier utilizes Karatsuba algorithm and Mastrovito approach to optimize polynomial multiplication and modular reduction, which lead to a better space and time tradeoff for all trinomials. Based on this work, we make two types of contributions: 1) We derive a new modular reduction formulation for constructing Mastrovito matrix associated with special types of pentanomials, i.e., Types I, II, and Type C.1 pentanomial. Through related formulations, we demonstrate that Type I pentanomial is less efficient than Type II because of a more complicated modular reduction under the same SPB; conversely, Type C.1 pentanomial is as good as Type II under generalized polynomial basis (GPB). 2) We introduce a new MK multiplier for Type II pentanomial. It is shown that our proposal is only one $T_{X}$ slower than the fastest quadratic multipliers for Type II pentanomial, but its space complexity is roughly 3/4 of those schemes. To the best of our knowledge, it is the first time for hybrid multiplier to achieve such a time delay bound.

A Crystal View on the Design of FIR Filter

In audio and video signal processing main element is the FIR filter. This paper presents complete information regarding the FIR filters. It also focuses on the design of FIR filters which provide low-area, energy-delay, low-power consumption, high-speed, low critical path, and low complexity. Implementation of FIR filters with different methods like memory-based VLSI architecture, filters for sampling rate conversion, linear phase FIR filters, optimal hybrid form FIR filters, Nyquist filters, hybrid multiplier less FIR filters, low complexity FIR filters, variable partition hybrid form FIR filters, area efficiency FIR filters are discussed in this paper. The objective of this paper to provide all related information regarding FIR filters at one platform.

Performance Analysis of a Low-Power High-Speed Hybrid Multiplier Circuit

Performance Analysis of a Low-Power High-Speed Hybrid Multiplier Circuit

Fog assisted task allocation and secure deduplication using 2FBO[formula omitted] and MoWo in cluster-based industrial IoT (IIoT)

Fog-assisted Internet-of-Things have dynamically received interest in the research community. There are more duplicate data transmitted over the Internet due to the rise in IoT devices. In this paper, task allocation and secure deduplication are implemented over four layers of Fog assisted Cluster-based Industrial IoT. IoT device layer used to sense data and mitigate security threats. Devices presented in this layer are registered to the cloud server using Elliptic Curve Cryptography based Hybrid Multiplier. Multi-Objective based Whale Optimization algorithm is accessible for cluster section. SHA-3 is presented in the fog layer for secure data deduplication. ECC HM private key is used for data encryption before transmitted the data. In cloud, layer indexing is constructed using Merkle Hash Tree. This is endeavored to provide query search results for IoT users at the service layer. The simulation results prove enhancement in average latency, user satisfaction, network lifetime, energy consumption, and security strength.

On the Complexity of Hybrid $n$ -Term Karatsuba Multiplier for Trinomials

The ${n}$ -term Karatsuba algorithm (KA) is an extension of 2-term KA, which can obtain even fewer multiplications than the original one. The existing ${n}$ -term Karatsuba hybrid $\textit {GF}(2^{m})$ multipliers rely on factorization of ${m}$ or ${m}-1$ , so that put a confinement to these schemes. In this contribution, we use a new decomposition ${m}={n}\ell +{r}$ , such that $0\leq {r} and $0\leq {r} , and propose a novel ${n}$ -term Karatsuba hybrid $\textit {GF}(2^{m})$ multiplier for an arbitrary irreducible trinomial ${x}^{m}+{x}^{k}+1, {m}\geq 2{k}$ . Combined with shifted polynomial basis, a new approach (other than Mastrovito approach) is introduced to exploit the spatial correlations among different subexpressions. We investigate the explicit space and time complexities, and discuss related upper and lower bounds. As a main contribution, the flexibilities of ${n}, \ell $ and ${r}$ make our proposal approaching optimal for any given ${m}$ . The space complexity can achieve to ${m^{2}}/{2}+{O}({\sqrt {11} {m}^{3/2}}/{2})$ , which roughly matches the best result of current hybrid multipliers for special trinomials. Meanwhile, its time complexity is slightly higher than the counterparts, but can be improved for a new class of trinomials. In particular, we demonstrate that the hybrid multiplier for ${x}^{m}+{x}^{k}+1$ , where ${k}$ is approaching $\frac {m}{2}$ , can achieve a better space-time trade-off than any other trinomials.

Efficient Bit-Parallel Multiplier for All Trinomials Based on n-Term Karatsuba Algorithm

Recently, hybrid multiplication schemes over the binary extension field GF(2m) based on nterm Karatsuba algorithm (KA) have been proposed for irreducible trinomials. Their complexities depend on a decomposition of m and the choice of a generation polynomial. However, these multipliers have some limitations on a decomposition of m or generation polynomial x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> + x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> + 1 such that m ≥ 2k. In this paper, we loosen such limited conditions. We present a new hybrid bit-parallel multiplier based on n-term KA for any irreducible trinomial x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> + x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> + 1 (0 k m), where m is decomposed as m = nm <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> + r with 0 r m0 and 1 n. (Here, various values for n, m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> and r may be chosen.) To this end, we generalize the previously proposed multiplication scheme for x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nm0+1</sup> +x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> +1 into x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nm0+r</sup> +x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> +1. We evaluate the explicit complexity of the proposed multiplier. Specific comparisons show that the proposed multiplier achieves the lowest space complexity with the same or lower time complexity among hybrid multipliers. Compared to the fastest multipliers, the time complexity of the proposed multiplier costs only TX higher while its space complexity is much lower (it has roughly 40% reduced space complexity), where TX is the delay of one 2-input XOR gate.