HSPICE Simulation Research Articles

Read Disturbance in Cross-Point Phase-Change Memory Arrays—Part II: Array Simulations Considering External Currents

In Part I of this study, we demonstrated that when a high-read current from phase-change memory (PCM) programmed at a high-SET current ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {SET}}{)}$ </tex-math></inline-formula> is achieved, melting dynamics in the chalcogenide layer are promoted, thus leading to read disturbances. Therefore, we analyzed additional external current sources that worsened the read disturbances by considering the PCM cell and additional selector and core circuits used in practical applications. By means of HSPICE simulations, the impact of two noticeable external overshoot and inrush currents generated during respective SET and read operations in one-selector and one-PCM (1S-1R) array was investigated. Our findings show that resistance-related components mainly affect the magnitude of the inflowing external current to the 1S-1R cell. The PCM can thus be easily heated up by the current, making the memory state vulnerable to the melting process. For these reasons, we showed that the disturbance primarily observed in the high <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {SET}}$ </tex-math></inline-formula> operated PCM can also occur even at low- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">${I}_{\text {SET}}$ </tex-math></inline-formula> settings, given the actual cross-point array environment. Finally, we explored the maximum achievable array size that ensures disturbance-free read endurance by quantifying the read current to examine the location wherein the melting occurs.

Crosstalk analysis of dielectric inserted side contact multilayer graphene nanoribbon interconnects for ternary logic system using unconditionally stable FDTD model

In the present work, for examining the performance of dielectric inserted side contact multilayer graphene nano ribbon (DSMLGNR), a novel Unconditionally Stable Finite-Difference Time-Domain (USFDTD) technique is proposed. This technique overcomes the constraint of courant stability condition prevailing in FDTD technique. The proposed mathematical model is highly time efficient and accurately analyzes the crosstalk effects induced among the coupled interconnect lines. The robustness of the USFDTD technique is verified by determining various performance metrics and justifying it with FDTD technique and HSPICE simulations. The obtained results are in accordance with HSPICE and the average percentage error is less than 1%. For performing the transient analysis, USFDTD model consumes 25% lesser time compared to FDTD technique. Furthermore, accuracy of the proposed model is validated by using Feature Selective Validation (FSV) tool.

Design and analysis of ternary delay flip-flop implemented with carbon nanotube field effect transistor

Flip-flops serve as fundamental memory storage elements in digital circuits, and their efficiency significantly affects overall circuit performance. The aim of this study is to create a D flip-flop based on ternary logic and evaluate its performance in comparison to flip-flops that have already been designed. The proposed D flip-flop design leverages Carbon Nanotube Field Effect Transistors (CNTFETs). CNTFETs offer unique properties that can enhance the speed and power efficiency of flip-flop design. To evaluate the performance of the proposed design, it was simulated using the HSPICE simulator with a 32 nm Stanford CNTFET model. The simulation parameters include a power supply voltage of 0.9 volts and an operating frequency of 1 GHz. These specific settings allow researchers to analyze the behavior and performance of flip-flops under realistic operating conditions. By comparing the simulation results of the proposed D flipflop with the performance of previously designed flip-flops, the improvements are assessed in terms of the speed and power consumption. The simulation results provide valuable insights into the efficiency, reliability, and responsiveness of the proposed design. The findings of this research contribute to the advancement of digital circuit design by introducing a novel D flip-flop based on ternary logic and CNTFET technology. The goal is to enhance the overall performance efficiency of digital circuits, particularly in applications where D flip-flops are used as building blocks such as shift registers.

Energy Efficient Circuit Design of Single Edge Triggered Ternary Shift Registers Using CNT Technology

With the miniaturization of digital integrated circuits, electronic systems with increased functionality and enhanced performance are preferred. Multi-valued logic design is a promising alternative that offers a higher number of data/information which leads to energy efficiency, higher information density and reduced circuit overheads in terms of interconnect complexity. Hence in this work multi-valued logic design benefits of increased computational capability and reduced interconnect complexity are being explored for the implementation of sequential elements viz. ternary shift registers. Carbon nanotube field-effect transistors(CNTFETs) unique feature of alteration of threshold voltage by variations in CNT diameter further favor its suitability to implement ternary logic designs. Here single-edge triggered ternary shift registers design methodology is presented using multiplexer based D-flip-flop cells. The design of D-flip-flops is performed using multiplexer based positive and negative latches. After this series connection of D-flip-flop is performed to construct serial input serial output and parallel input serial output registers. The parallel input serial output registers can operate in two modes of loading and shifting and three different configurations of AND-OR logic, NAND logic and latch based selection circuitry are proposed. For performance analysis Synopsis HSPICE simulations are conducted using the 32nm CNTFET Stanford model. According to simulation results, for the proposed ternary shift registers maximum reduction in power consumption and energy consumption of more than 80% are obtained as compared to recent counterparts.

Design and Optimization of Ultradeep Submicron CMOS Inverter Using a Unified All Regional MOSFET Model

Complementary Metal Oxide Semiconductor (CMOS) has always remained the dominant integrated circuit technology specifically for designing digital circuits. This paper examines the modelling (utilizing $\alpha$-power based MOSFET model), simulation (utilizing HSPICE simulation) and optimization (utilizing Particle Swarm Optimization (PSO) and Artificial Bee Colony (ABC) techniques) of ultradeep submicron CMOS based digital inverter, performs insightful analysis and extracts formulas for the optimal transistor sizing. Additionally, the study serves as an implementation forum for the thermal analysis of transient characteristics of CMOS inverters at the ultradeep submicron technology node (at 300K and 400K). The results lie within the acceptable range of 1-10\%.

The Design of Digital System with CSA

In this paper, we present a carry skip adder (CSKA) structure that has a higher speed yet lower energy consumption compared with the conventional one. The speed enhancement is achieved by applying concatenation and incrementation schemes to improve the efficiency of the conventional CSKA (Conv-CSKA) structure. In addition, instead of utilizing multiplexer logic, the proposed structure makes use of AND-OR-Invert (AOI) and ORAND-Invert (OAI) compound gates for the skip logic. The structure may be realized with both fixed stage size and variable stage size styles, wherein the latter further improves the speed and energy parameters of the adder. Finally, a hybrid variable latency extension of the proposed structure, which lowers the power consumption without considerably impacting the speed, is presented. This extension utilizes a modified parallel structure for increasing the slack time, and hence, enabling further voltage reduction. The proposed structures are assessed by comparing their speed, power, and energy parameters with those of other adders using a 45-nm static CMOS technology for a wide range of supply voltages. The results that are obtained using HSPICE simulations reveal, on average, 44% and 38% improvements in the delay and energy, respectively, compared with those of the Conv-CSKA. In addition, the power–delay product was the lowest among the structures considered in this paper, while its energy–delay product was almost the same as that of the Kogge–Stone parallel prefix adder with considerably smaller area and power consumption. Simulations on the proposed hybrid variable latency CSKA reveal reduction in the power consumption compared with the latest works in this field while having a reasonably high speed.

Optimization Techniques for Reliable Low Leakage GNRFET-Based 9T SRAM

We present a low-leakage graphene nano-ribbon transistors (GNRFETs)-based static random access memory (SRAM) cell in 16nm technology that operates near the sub-threshold region in this study. In comparison to conventional Si-CMOS technology, the proposed cell improves read stability and writeability by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$2.67\mathbf {\times }$ </tex-math></inline-formula> and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4.14\mathbf {\times }$ </tex-math></inline-formula> , respectively. The proposed cell considerably outperforms the existing 9T SRAMs cell in terms of power consumption, latency, read stability, and write-ability, according to the HSPICE simulation. In addition, at the low supply voltage of 325mV, the multi-threshold approach and transistor optimizations are used to improve the read static noise margin (RSNM). The proposed cell’s overall power consumption is lowered by <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$4161\mathbf {\times }$ </tex-math></inline-formula> when compared to a conventional 6T SRAM cell while using the multi-threshold approach in the write port. Device optimization and the multi-threshold approach, which enhances read and write performance, can considerably minimize read and write delays.

A Universal Electronically Controllable Memelement Emulator Based on VDCC with Variable Configuration

In this paper, a universal fractional order memelement (FOME) emulator is proposed based on the use of a voltage differentiating current conveyor (VDCC) as active block. The emulation circuit was implemented without an analog voltage multiplier and with only one type of grounded passive element—capacitors. Specially designed switching networks allow controlling the type of memelement and the emulator mode—floating or/and grounded, electronically controlled (by changing the bias voltage of the VDCC) FOMEs. The proposed emulator was theoretically analyzed, and the influence of possible non-idealities and parasitic effects was also been analyzed to reduce the undesirable effects by selecting the passive circuit elements. The proposed designs are very simple compared to most of the designs available in the literature and can operate in a wide frequency range (up to 50 MHz) and also satisfy the non-volatility test. All realized memelements can be used in incremental and decremental modes as well as in inverse configuration. The performance of the circuit was verified by HSPICE simulations using 0.18 μm TSMC process parameters and ±0.9 V power supply. The proposal is also supported by experimental results with off-the-shelf components (LM13700 and one AD844) in order to confirm the proposed solution’s workability.

A compact circuit-level model for single-event burnout in SiC power MOSFET devices

This paper presents a compact circuit-level model for single-event burnout (SEB) in silicon carbide (SiC) metal-oxide field-effect transistors (MOSFETs). Key parameters of the equivalent circuit model of the MOSFET are analyzed and determined in detail, including nonlinear parasitic drain-source capacitance and nonlinear parasitic gate-drain capacitance. The effect of the parasitic bipolar junction transistor is considered and an iteratively optimized double-exponential current source is used to simulate the transient power current generated by incident heavy ions. The equivalent circuit model of the MOSFET is verified by comparing the SPICE simulation curves, TCAD simulation curves, and the curves in the SiC power double trench MOSFET’s datasheet (SCT3080KL). Then, the SEB is caused by heavy ions at various incident positions, linear energy transfer values, drain-source voltage (V ds), and gate-source voltage (V gs) using the TCAD and HSPICE simulations. Simulation results on the SPICE model coincide with the TCAD simulation results. Moreover, this compact model is used to predict the SEB threshold for devices with higher breakdown voltage ratings.

Diode Connected Transistor-Based Low PDP Adiabatic Full Adder in 7 nm FINFET Technology for MIMO Applications

Full adders are a core component and play an essential role in the design of contemporary very-large-scale integration (VLSI) integrated circuits. Low-power, high-speed adder design has been the subject of numerous different sorts of research. The never-ending process is still in progress. The saturation point for MOS-based VLSI circuit design has been reached. As a consequence, many additional issues arise when MOS devices are scaled down to the nanoscale range, including an increase in leakage power and a vulnerability to PVT variation. Hence, MOSFET alternatives have been looked after by VLSI industries. Future nanoscale VLSI circuits would benefit greatly from the use of FINFETs in place of MOS transistors. In this paper, two diode-connected transistors-based low power, high speed, and low-power–delay product (PDP) adiabatic logic full adders are proposed using 7 nm technology. DCT TSAA-I, DCT TSAA-II, DCT TCAA-I, and DCT TCAA-II are the names of the proposed structures. Power, speed, and power–delay product (PDP) performance of the proposed adders are compared with those of traditional full adders. According to the simulation outcomes, the proposed adder architectures offer the least PDP in comparison to the adders taken into consideration. On power and delay, the impact of changing variables like temperature, supply voltage, load capacitance, and frequency is seen. A 7 nm FINFET model has been used in the simulations, which were conducted using the Hspice simulation tool.

A High Performance and Low Power Triple-Node-Upset Self-Recoverable Latch Design

The charge sharing effect is becoming increasingly severe due to the continuous reduction of semiconductor process feature size. In the nanoscale digital circuit, the probability of triple-node upset (TNU) is increasing, which seriously affects the reliability of the circuit. To improve the reliability of the digital circuit, this paper presents an optimized TNU self-recoverable latch (HLTNURL). This latch consists of three dual-node-self-recoverable dual interlocked storage cells (DNSR-DICE) and one clock-gating C-element. Whenever any three nodes invert, the latch is able to self-recover to its correct logical values. The HSPICE simulation results indicate that this latch enables full self-recovery of TNU in all cases. In comparison with existing TNU self-recoverable latches, the proposed HLTNURL latch is able to reduce the power dissipation, delay, area overhead, and area-power-delay product (APDP) by 32.41%, 79.73%, 1.32%, and 88% on average. In addition, the HLTNURL latch proposed in this paper has high reliability and low sensitivity to process, voltage, and temperature (i.e., PVT) variations.

Design of Ternary Logic Circuits using Pseudo N-type CNTFETs

In this paper, a novel method is presented to design ternary logic circuits for nanoelectronics applications. The ternary logic is a best alternative to the binary logic because it offers reduced interconnects, faster operating speed and reduced chip area. The digital logic circuit designs are developed using Pseudo N-type carbon nanotube field effect transistors (CNTFETs). The threshold voltage of CNTFETs is altered by the CNT diameter that is defined by the chirality vector. The ternary inverters such as standard inverter (SI), positive inverter (PI) and negative inverter (NI) and ternary basic gates such as AND, NAND, OR and NOR gates are designed. Furthermore, the half adder circuits developed which assists to develop complex circuit schematics. The proposed ternary schematics are designed and simulated using the HSPICE simulator. Moreover, the performance of the proposed circuits are investigated in terms of delay, power dissipation and power delay product (PDP) and compared with the existing circuits. It is observed that the proposed circuits show average performance improvement up to 47.48% over the existing circuits.

Neoteric Design Power Sustained 3-Bit Asynchronous Counter Using CNFET Based MCML Topology

Leading digital circuits namely register, flipflops, state machines and counters drive operational aspects and potential applications in Integrated Circuit (IC) industry. MOS Current Mode Logic (MCML) based implementations with rapid response and simultaneous generation of complemented output is all set to become indispensable in nano regime industry. This paper attempts to optimize and address performance-based analysis of digital circuits namely NAND, D flipflop and 3-bit asynchronous counter by practicing MCML based implementation. These circuits are contemplated on four design parameters namely delay (t_p), power (pwr), Power Delay Product (PDP) and Energy Delay Product (EDP). This research focuses on relative analysis and emanate a salient optimal application of Complementary Metal-Oxide-Semiconductor (CMOS) and Carbon Nanotube Field Effect Transistor (CNFET) based 3-bit asynchronous counter. In addition to this, the two configurations of the MCML counter are then compared against applied V_DD at 16-nm technology nodes using HSPICE simulator. CNFET based 3-bit MCML counter is observed to be much faster (9.75x), significant improvement in gross power dissipation (11.93x), material refinement in PDP and EDP (116.39x and 1165x) respectively as compared to the conventional counterpart. Therefore, CNFET based implementations comes to the fore as resilient technology supporting high level integration in nano scale regime.

Withdrawal: P. A. Harsha Vardhini and M. Makkena (2022), Design and Comparative Analysis of On‐Chip Sigma Delta ADC for Signal Processing Applications. Advanced Control for Applications: Engineering and Industrial Systems. Accepted Author Manuscript e82. https://doi.org/10.1002/adc2.82

Advent in VLSI technology made digital signal processing to take over analog signal processing. Analog to digital converter plays a vital role in modern digital processing applications. Sigma delta analog to digital converter architecture being digital dominant architecture is much suitable for signal processing applications. This paper presents the design of a low pass continuous time sigma delta analog to digital converter on-chip architecture suitable for signal processing applications with a very few passive components connected externally to FPGA. Schematic level architecture of high-speed comparator working at a differential swing which is not allowed by standard differential pads is designed. By applying various differential swings at the input to LVPECL, the performance and power is analyzed. High performance comparator schematic is designed for On-chip Continuous-time Sigma-delta ADC architecture. Simulations are carried out to verify the maximum input frequency for given RC values. Xilinx provided Spartan 6 I/O pad and package SPICE models are used. Power analysis is carried out with LVPECL logic family based differential buffers along with external RC circuit. The analog and digital sections simulations along with mixed signal simulations at different stages are performed. Power and performance analysis are carried out using H-Spice and Questasim simulations.

Bitwise Logical Operations in VCMA-MRAM

Today’s technology demands compact, portable, fast, and energy-efficient devices. One approach to making energy-efficient devices is an in-memory computation that addresses the memory bottleneck issues of the present computing system by utilizing a spintronic device viz. magnetic tunnel junction (MTJ). Further, area and energy can be reduced through approximate computation. We present a circuit design based on the logic-in-memory computing paradigm on voltage-controlled magnetic anisotropy magnetoresistive random access memory (VCMA-MRAM). During the computation, multiple bit cells within the memory array are selected that are in parallel by activating multiple word lines. The designed circuit performs all logic operations-Read/NOT, AND/NAND, OR/NOR, and arithmetic SUM operation (1-bit approximate adder with 75% accuracy for SUM and accurate carry out) by slight modification using control signals. All the simulations have been performed at a 45 nm CMOS technology node with VCMA-MTJ compact model by using the HSPICE simulator. Simulation results show that the proposed circuit’s approximate adder consumes about 300% less energy and 2.3 times faster than its counterpart exact adder.

The Detection of Open and Leakage Faults for Prebond TSV Test Based on Weak Current Source

During the manufacturing process of three-dimensional integrated circuits (3-D ICs), many defects may occur in through-silicon vias (TSVs). These defects affect the integrity of the signal passing through TSVs, therefore detecting these defects in the early production stage is crucial. This article proposed a built-in-self-test (BIST) method with a simple test structure and easily implemented fault detection process. Due to the fact that the defects in TSVs influence the charge/discharge speed of TSVs’ equivalent capacitance, a weak current source is designed as the central part of the proposed test structure, which can measure the TSVs’ charge/discharge speed and quantify it using digital values. The effectiveness and robustness of the proposed method is validated by HSPICE simulation. The minimum measurable fault, test time, and test circuit area are also assessed in this article. The simulation results show that the method this article proposed can detect weaker faults, compared with the traditional test methods.

A Reference Source Circuit Design for Voltage Controlled Oscillator Chips

The basic principle and typical structure of the bandgap voltage reference source are introduced in detail in this paper. The performance index of the bandgap voltage reference is analyzed. The core circuit of a bandgap voltage reference source with good temperature characteristics and a high power supply rejection ratio (PSRR) is designed, in which a two-stage differential operational amplifier with a buffer stage is used, a start-up circuit without a capacitor is used to reduce the start-up time, and a common beta multiplication self-bias circuit is used to attenuate the effects of the power supply voltage. It is shown from the final HSPICE simulation results that the reference voltage temperature coefficient is approximately 7 ppm/°C within the range of -20 to 80°C in temperature, and the average PSRR can reach more than −56 dB within the range of 1 Hz to 10 kHz in frequency.

Image processing with high-speed and low-energy approximate arithmetic circuit

Nowadays there are plenty of compute-intensive algorithms that are carried out at the edge. Therefore, it is necessary to design low-energy and high-speed circuits. Approximate computing (AC) is an emerging paradigm that can be used in error-resilient applications such as multimedia processing. In this paper, a novel approximate full adder design is proposed with the aim of latency and energy consumption reduction at the cost of producing some errors at the output. The proposed design uses pass transistor and transmission gate logic styles to achieve these aims. The proposed cell and referenced circuits are applied in a vast range of simulation conditions including power supply, ambient temperature, and load variations. Moreover, the constancy of the proposed cell concerning the process variations of carbon nanotubes (CNTs) is studied. All circuits are implemented at the transistor level using carbon nanotube field-effect transistor (CNFET) technology. Experimental results based on HSPICE simulation indicate the superiority of the proposed cell in terms of latency, power-delay product (PDP), and energy-delay product (EDP) criteria against state-of-the-art designs. Moreover, at the application level, image blending is used to study the accuracy metrics such as peak signal-to-noise ratio (PSNR) and structural similarity (SSIM) quantitative metrics. Finally, the PDP, PSNR, and SSIM metrics are simultaneously taken into account as a figure of merit (FOM) to trade-off between circuit and application-level metrics. Quantitative results confirm the better functionality of the proposed approximate full adder cell compared to its counterparts.

Multi-valued logic arbiter PUF designs based on CNTFETs

Arbiter physical unclonable functions (APUFs) are integrated circuits (ICs) capable of storing secret keys spontaneously, which makes them a great fit for electronic device authentication and key generation applications. In this work, we propose two novel designs of multi-valued logic (MVL) APUFs using carbon nanotube field effect transistors (CNTFETs). Using MVL will enhance the APUF security by increasing the size of challenge-response pairs. The proposed designs are investigated under the 32nm CNTFET standard model library using HSPICE simulations. On average, the randomness in the ternary and the quaternary APUF responses are 32.75% and 24.47% in the worst case respectively, which are near the ideal randomness of 33.33% and 25%. Also, we analyzed the reliability of the proposed APUFs in different temperatures and supply voltages. Additionally, we implemented and analyzed the proposed designs using the 14nm CNTFET standard model library to ensure that our designs maintain stability.

A High-Frequency Multi-Mode Universal Filter for GHz Applications in CNFET Technology

This paper presents a new circuit structure of a multi-mode active filter, using only 16 transistors and 2 grounded capacitors in carbon nanotube field-effect transistor (CNFET) technology which is biased at [Formula: see text][Formula: see text]V supply. The proposed multi-input, single-output (MISO) filter has the capability of working as low-pass, band-pass, high-pass, band-stop and all-pass filters in all the operating modes (voltage, current, transconductance and transresistance). In addition, the quality factor ([Formula: see text]) parameter can be tuned electronically independent of the center frequency ([Formula: see text]). The HSPICE simulation results show that the proposed filter consumes only 971[Formula: see text][Formula: see text]W at 1[Formula: see text]GHz center frequency, assuming [Formula: see text][Formula: see text]pF and the nanotube pitch parameter of ([Formula: see text] nm) and the chiral vector of (22,0), while the number of nanotubes is considered as [Formula: see text] for all the transistors. Moreover, the main circuit performances such as the center frequency and the power consumption of the circuit vary by 5.4% and 11.6%, respectively, for the standard temperature variation.